Does mmap() align on 32-bit boundary? (Re-posing)

QNX Newsgroups (Archives) qdn.public.qnxrtp.newuser
1

( I posted this last week, it appeared for one day, but for some reason
disappeared. Re-posting… )

–

Hi,

I am writing a driver and my DMA controller requires that the address of DMA
transfers be aligned on a 32-bit boundary. Does mmap() return an address
that is 32-bit aligned?

Under DOS, the old driver was doing the following:

#define data_transfer_buf_size 32768U
ubyte data_transfer_buf[32771U]; // 3 bytes bigger
ubyte *ptr_data_transfer_buf;

/* check the data_transfer_buf alignment and fix it if needed */
if (FP_OFF(data_transfer_buf) & 0x01)
ptr_data_transfer_buf = &data_transfer_buf[0] + 3;
else
if (FP_OFF(data_transfer_buf) & 0x02)
ptr_data_transfer_buf = &data_transfer_buf[0] + 2;
else
if (FP_OFF(data_transfer_buf) & 0x03)
ptr_data_transfer_buf = &data_transfer_buf[0] + 1;
else
ptr_data_transfer_buf = &data_transfer_buf[0];


Under QNX, I am doing the following:

(attached q1.c)

Is this correct? Do I need it, or does mmap() allocate the DMA buffer
correctly aligned?

Thanks!
Alain Achkar





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M/3T]/3T]/3T]/3T]/3TJ+PT*#0IC:&%RB @("!T;7!?861D<CL-“F-H87(J
M(” @(’-C<FEP=’-?861D<CL-"@T<&%D9’)?=" @<&AY<U]T;7!?861D<CL-
M"G!A9&1R7W0@(’!H>7-?<V-R:7!T<U]A9&1R.PT*#0H-“G1Y<&5D968@=6YS
M:6=N960@;&]N9R!53$].1SL-”@T54Q/3D<@4T-225!46UT@/2![#0H@(#!X
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M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM
M+2TM+2TMB-“B\J($QO860@4T-225!44R!A;F0@86QI9VX@;VX@82!$5T]2
M1”!B;W5N9&%R>2 @(" @(" @(" @(" @(" @(" @(" @(" @(" @(" @B-
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M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TMB-"@T=F]I9”!L
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end

2

Alain Achkar <aachkar@storagequest.com> wrote:

( I posted this last week, it appeared for one day, but for some reason
disappeared. Re-posting… )

Ok, here’s a copy of the answer I posted:

Alain Achkar <aachkar@storagequest.com> wrote:

Hi,

I am writing a driver and my DMA controller requires that the address of DMA
transfers be aligned on a 32-bit boundary. Does mmap() return an address
that is 32-bit aligned?

Yes. You also need physically contiguous – but you have MAP_PHSY|MAP_ANON
which will give you that. Since you are x86, you will also want MAP_NOX64K
and if it is an ISA device you will want MAP_BELOW16M.

To get the physical address, I would suggest mem_offset() (which is
documented) rather than mphys() which isn’t.

-David

–
QNX Training Services
dagibbs@qnx.com

3

Actually, in my q1.c, I defined a fuction called mphys() which uses
mem_offset(). I did not know that mphys() was an undocumented function.

Now, regarding the flags, I am using MAP_PHSY|MAP_ANON.
The card is a PCI, so I don’t need MAP_BELOW16M.

What is not clear to me from the documentation is the use of MAP_NOX64K.
When do I need it? What if the memory I am allocating is greater than 64K ?

The chip I am working with (SYM53C875) does not say anything about 64K
boundaries. It has a MOVE instruction which can move 2^24 bytes (16MBytes)
in one instruction from memory to the SCSI bus, which looks like this:

MOVE FROM data_buf, WITH DATA_IN

The bottom line, is, can I allocate 16MB with mmap() and do I need to worry
about 64K boundaries?

Thanks again!
Alain


“David Gibbs” <dagibbs@qnx.com> wrote in message
news:9gnsne$jrv$2@nntp.qnx.com…

Alain Achkar <> aachkar@storagequest.com> > wrote:
( I posted this last week, it appeared for one day, but for some reason
disappeared. Re-posting… )

–

Ok, here’s a copy of the answer I posted:

Alain Achkar <> aachkar@storagequest.com> > wrote:
Hi,

I am writing a driver and my DMA controller requires that the address of
DMA
transfers be aligned on a 32-bit boundary. Does mmap() return an
address
that is 32-bit aligned?

Yes. You also need physically contiguous – but you have
MAP_PHSY|MAP_ANON
which will give you that. Since you are x86, you will also want
MAP_NOX64K
and if it is an ISA device you will want MAP_BELOW16M.

To get the physical address, I would suggest mem_offset() (which is
documented) rather than mphys() which isn’t.

-David

–
QNX Training Services
dagibbs@qnx.com

4

Alain Achkar <aachkar@storagequest.com> wrote:

Now, regarding the flags, I am using MAP_PHSY|MAP_ANON.
The card is a PCI, so I don’t need MAP_BELOW16M.

Ok – just warning you as you didn’t specify.

What is not clear to me from the documentation is the use of MAP_NOX64K.
When do I need it? What if the memory I am allocating is greater than 64K ?

If allocating more than 64K, the allocated chunk will, I think, start on
a 64K boundary, but will be allowed to cross.

The chip I am working with (SYM53C875) does not say anything about 64K
boundaries. It has a MOVE instruction which can move 2^24 bytes (16MBytes)
in one instruction from memory to the SCSI bus, which looks like this:

MOVE FROM data_buf, WITH DATA_IN

The bottom line, is, can I allocate 16MB with mmap() and do I need to worry
about 64K boundaries?

I don’t know enough about PC DMA at the hardware level to say for sure –
I know that the 64K boundary/aligned issue was (supposedly) need for PC
DMA. It may be an issue for the AT DMA controller, and a bus-master card
may be ok – or it may just be assumed that if you’re doing DMA, you’ll
know that, and the card’s docs don’t specify.

-David

QNX Training Services
dagibbs@qnx.com

5

Hi,
I worked whith PC/AT DMA and ISA cards some years ago. The standard DMA
controller (Intel-8237A, single in XT and first in AT) has 16-bit address
registers and 4-bit page registers. Since the current address is a 16-bit
value, it is not possible to cross a 64K boundary with DMA operation. In
addition to the four 8-bit channels of the XT, the AT adds a second DMA
controller (Intel 8237A-5 by cascading) which supports 16-bit DMA channels.
The second DMA controller has 8-bit page registers, but address registers
consist 16 bits. The current address in DMA operation is calculated by :
page_reg<<16+addr_reg<<1. So the max. page size is 128 K (64 K words) and
DMA transfers must not cross a 128K boundary.
Don’t care about boundaries if your chip has no limitations above.

Regards,
Eduard.