Wayne Fisher <wayne.fisher@focusautomation.com> wrote:
: “Brian Stecher” <bstecher@qnx.com> wrote in message
: news:9bk0mt$sk9$1@nntp.qnx.com…
:> Wayne Fisher <wayne.fisher@focusautomation.com> wrote:
:> > But, if QNX6 uses 64bits behind the MMU than it’s theoretically possible
:> > that a full 32 bits of addressing could be allocated to PCI devices
:> > (assuming, of course, that the CPU itself can address more than 4GB).
:> > However, with processes limitted to 4GB of address, no one process could
:> > address all 32bits worth of the PCI bus.
:>
:> The current implementation only supports 32 bits of physical address. This
:> will be increased in the future, but there’s no time frame for it yet.
: Ok, I think that I’m getting the picture. It goes something like this:
: 4096 MB Max. physical address range.
: -512 MB Reserved for OS (for at least some of the supported
: processors)
: -M MB Size of physical memory.
: ---------
: P MB Space left for PCI.
Hi Wayne,
here’s a (hopefully) more detailed answer to your question, with some
specifics on PowerPC.
First, the virtual address space of a given process is (of course) 4GB,
of which the bottom 1GB is taken up by the kernel and related supervisor
mappings. So 3GB is available for each process.
On the hardware side, the PowerPC has a 32 bit physical address bus (except
the 7450, which has 36 bits). So the processor itself can address up
to 4GB of physical memory. Virtual “process” addresses (pointers) in the
TLB and in the MMU get translated to 32 bits of physical addresses.
Now, where things get a little more complicated is when you put a bridge
in the system. The bridge does CPU<–>PCI translation, and normally the
PowerPC bridges have fixed-size windows (in the 32 bit physical world) of
where memory, PCI memory, PCI I/O, ROM etc. go. As an example, the MPC107
bridge (probably what you’re using) has
0-1G for RAM
1-2G reserverd
2G-~3.5G PCI Memory
and then further windows for PCI I/O, ROM etc.
So the limit on PCI memory in that case is 1.5GB total,
quite a bit less than what the processor can address. Further, the memory
map can usually not be modified (this is a CHRP memory map, BTW). Mapping
512MB in multiple processes or 1.5GB in a given process would certainly be
possible, and would not hit any limits except the RAM needed for MMU
structures.
I hope that answers the question… as an aside, inside the kernel, we keep
track of physical addresses using 64 bit variables. This allows us to
address more than 4GB physical on processors that support this (MIPS R4000,
most notably). Some day, it may also be supported on some other processors.
Sebastien
Sebastien Marineau
Netcom Architect
QNX Software Systems Ltd
(613) 271-9336
sebastien@qnx.com