QNX, cPCI, Linux...

QNX Newsgroups (Archives) qdn.public.qnxrtp.os
1

Hi…

I have a cPCI cpu board running Neutrino 6.1, and then I have a second
cPCI cpu board that runs a proprietary software on Linux (which we are
forbidden to port to QNX).

Can the two boards share the same cPCI back pane? Has any body done
this before?

I appreciate your help. Thanks…

Best Regards…

Miguel.


\

my opinions are mine, only mine, solely mine, and they are not related
in any possible way to the institution(s) in which I study and work.

Miguel Simon
Research Engineer
School of Aerospace and Mechanical Engineering
University of Oklahoma
http://www.amerobotics.ou.edu/
http://www.saic.com

2

Miguel Simon wrote:

Hi…

I have a cPCI cpu board running Neutrino 6.1, and then I have a second
cPCI cpu board that runs a proprietary software on Linux (which we are
forbidden to port to QNX).

Can the two boards share the same cPCI back pane?

There are so called slave CPUs, which allow multi processor
configurations for cPCI.

Let the master CPU run QNX6 and use LINUX on a slave CPU … IPC via
shared memeory.

Armin

3

“Armin Steinhoff” <a-steinhoff@web._de> wrote in message
news:3B76A62D.905EFD59@web._de…

Miguel Simon wrote:

Hi…

I have a cPCI cpu board running Neutrino 6.1, and then I have a second
cPCI cpu board that runs a proprietary software on Linux (which we are
forbidden to port to QNX).

Can the two boards share the same cPCI back pane?

There are so called slave CPUs, which allow multi processor
configurations for cPCI.

Let the master CPU run QNX6 and use LINUX on a slave CPU … IPC via
shared memeory.

Err, what do you mean by shared memory Armin? May be slave board can be can
be mapped into master’s PCI address space, but that isn’t exactly ‘shared
memory’ is it?

Also if those boards are both ‘master’ boards they still can be in same
backplane if that is ‘cPCI hotswap backplane’. Such backplanes have 2
‘domains’, each containing 1 CPU board. Slots in each domain may belong to
either (but not both at the same time) of CPU boards, that is controlled by
hot-swap controllers and system BIOS.

  • igor
4

Igor Kovalenko wrote:

“Armin Steinhoff” <a-steinhoff@web._de> wrote in message
news:3B76A62D.905EFD59@web._de…


Miguel Simon wrote:

Hi…

I have a cPCI cpu board running Neutrino 6.1, and then I have a second
cPCI cpu board that runs a proprietary software on Linux (which we are
forbidden to port to QNX).

Can the two boards share the same cPCI back pane?

There are so called slave CPUs, which allow multi processor
configurations for cPCI.

Let the master CPU run QNX6 and use LINUX on a slave CPU … IPC via
shared memeory.


Err, what do you mean by shared memory Armin?

Shared memory means memory which is shared by two processes …

May be slave board can be can be mapped into master’s PCI address space, but that isn’t exactly ‘shared
memory’ is it?

Err, not the whole ‘slave board’ can be mapped … you can map some
memory reagions of the slave board into the memory of the master
board.

Also if those boards are both ‘master’ boards they still can be in same
backplane if that is ‘cPCI hotswap backplane’.

I didn’t talk about two master boards. AFAIK … the multi
processor
backplane concept of cPCI allows only one master CPU board and
several slave CPU boards (using non transparent PCI bridges).

Such backplanes have 2
‘domains’, each containing 1 CPU board. Slots in each domain may belong to
either (but not both at the same time) of CPU boards, that is controlled by
hot-swap controllers and system BIOS.

You are talking about the Motorola specific ‘multi processor
backplane’ implementation ??

Armin

5

“Armin Steinhoff” <a-steinhoff@web._de> wrote in message
news:3B779450.3C35F49D@web._de…

Err, what do you mean by shared memory Armin?

Shared memory means memory which is shared by two processes …

Thanks for lesson, but I hoped for different answer. I wanted to know what
do you mean by ‘shared memory between master and slave CPU boards’.

May be slave board can be can be mapped into master’s PCI address space,
but that isn’t exactly ‘shared
memory’ is it?

Err, not the whole ‘slave board’ can be mapped … you can map some
memory reagions of the slave board into the memory of the master
board.

Yes, that’s what I thought. But when you say ‘IPC via shared memory’ you
make it sound too simple, like memory is common between 2 boards. I think
what you’re talking will probably require some sort of driver.

Such backplanes have 2
‘domains’, each containing 1 CPU board. Slots in each domain may belong
to
either (but not both at the same time) of CPU boards, that is controlled
by
hot-swap controllers and system BIOS.

You are talking about the Motorola specific ‘multi processor
backplane’ implementation ??

I don’t think there is standard for that thing yet. Motorola has such
implementation and some other vendors as well. I believe they all allow 2
master boards, in one way ot another.

  • igor
6

Igor Kovalenko wrote:

“Armin Steinhoff” <a-steinhoff@web._de> wrote in message
news:3B779450.3C35F49D@web._de…


Err, what do you mean by shared memory Armin?

Shared memory means memory which is shared by two processes …


Thanks for lesson, but I hoped for different answer. I wanted to know what
do you mean by ‘shared memory between master and slave CPU boards’.

Shared memory means memory which is shared by two processes …
running at the master and slave board.

May be slave board can be can be mapped into master’s PCI address space,
but that isn’t exactly ‘shared memory’ is it?

Err, not the whole ‘slave board’ can be mapped … you can map some
memory reagions of the slave board into the memory of the master
board.

Yes, that’s what I thought. But when you say ‘IPC via shared memory’ you
make it sound too simple, like memory is common between 2 boards. I think
what you’re talking will probably require some sort of driver.

No … I’m talking about IPC from a raw conceptual viewpoint.
It’s up to everyone’s fantasy how this can be implemented between
QNX/LINUX using shared memory … there are several approaches.

Armin

7

“Armin Steinhoff” <a-steinhoff@web._de> wrote in message
news:3B784F04.A913942B@web._de…

No … I’m talking about IPC from a raw conceptual viewpoint.
It’s up to everyone’s fantasy how this can be implemented between
QNX/LINUX using shared memory … there are several approaches.

That is very safe and convinient viewpoint, I shall adopt it.

  • Igor
8

Hi…

Thanks for the replies. I have learned from your discussion, but I not
able to add too much more…

Igor Kovalenko wrote:

“Armin Steinhoff” <a-steinhoff@web._de> wrote in message
news:3B779450.3C35F49D@web._de…


Err, what do you mean by shared memory Armin?

Shared memory means memory which is shared by two processes …


Thanks for lesson, but I hoped for different answer. I wanted to know what
do you mean by ‘shared memory between master and slave CPU boards’.

There may be a third board with memory in it. This memory can be shared
by any body on the backplane. At least this is my understanding. Also,
there is something called ‘reflective memory’ which I think is hardware
implemented. My understanding is that you write to this memory, and the
reflective memory board detects this and takes care of it. This would
be the way I would like to go, but I wonder about the drivers for Nto
which I am sure are non-existent.

May be slave board can be can be mapped into master’s PCI address space,
but that isn’t exactly ‘shared
memory’ is it?

Err, not the whole ‘slave board’ can be mapped … you can map some
memory reagions of the slave board into the memory of the master
board.

Yes, that’s what I thought. But when you say ‘IPC via shared memory’ you
make it sound too simple, like memory is common between 2 boards. I think
what you’re talking will probably require some sort of driver.

Actually, memory can indeed be common to the two boards via a third
memory board. But Igor is right in that this would require a driver
which may not exist for Nto -the Linux side may have a driver that I may
both utilize and port.

Such backplanes have 2
‘domains’, each containing 1 CPU board. Slots in each domain may belong
to
either (but not both at the same time) of CPU boards, that is controlled
by
hot-swap controllers and system BIOS.

You are talking about the Motorola specific ‘multi processor
backplane’ implementation ??

I don’t think there is standard for that thing yet. Motorola has such
implementation and some other vendors as well. I believe they all allow 2
master boards, in one way ot another.

This was my original question, and you have answered in some way. Also
I read in a cPCI magazine that this is possible now. The bottom line,
however, seems that I will have to try and dive into it myself.

  • igor

–

my opinions are mine, only mine, solely mine, and they are not related
in any possible way to the institution(s) in which I study and work.

Miguel Simon
Research Engineer
School of Aerospace and Mechanical Engineering
University of Oklahoma
http://www.amerobotics.ou.edu/
http://www.saic.com

9

Miguel Simon wrote:

Hi…

Thanks for the replies. I have learned from your discussion, but I not
able to add too much more…

Igor Kovalenko wrote:

“Armin Steinhoff” <a-steinhoff@web._de> wrote in message
news:3B779450.3C35F49D@web._de…


Err, what do you mean by shared memory Armin?

Shared memory means memory which is shared by two processes …


Thanks for lesson, but I hoped for different answer. I wanted to know what
do you mean by ‘shared memory between master and slave CPU boards’.

There may be a third board with memory in it. This memory can be shared
by any body on the backplane. At least this is my understanding.

The trick with the CPCI multiprocessor backplanes is based on the
non-transparent PCI bridges. (BTW … the only vendor is INTEL →
standard ??)
The slave CPU boards and its memory are not visible for the master
CPU board … but the slave CPU can map a memory section into to the
memory of the master (by programming the non-transparent PCI
bridge).

Also … the slave CPU boards are seen from the master site as
(very) intelligent IO boards.

Also, there is something called ‘reflective memory’ which I think is hardware
implemented.
My understanding is that you write to this memory, and the
reflective memory board detects this and takes care of it. This would
be the way I would like to go, but I wonder about the drivers for Nto
which I am sure are non-existent.

Reflective memory is used between buses (or systems). Most of the
products (e.g. VMIC) have LINUX support.
The implementation of the QNX support is not rocket sience (I did it
for a VMIC board).

May be slave board can be can be mapped into master’s PCI address space,
but that isn’t exactly ‘shared
memory’ is it?

Err, not the whole ‘slave board’ can be mapped … you can map some
memory reagions of the slave board into the memory of the master
board.

Yes, that’s what I thought. But when you say ‘IPC via shared memory’ you
make it sound too simple, like memory is common between 2 boards. I think
what you’re talking will probably require some sort of driver.

Actually, memory can indeed be common to the two boards via a third
memory board. But Igor is right in that this would require a driver
which may not exist for Nto -the Linux side may have a driver that I may
both utilize and port.

You don’t need a driver in order to access memory … isn’t it ?

Armin