What is the preferred way of accessing 16 physical hardware buffers on a PCI
card (through a PIC 9050 controller) using the QNX resource manager
The limitations are as follows: Each buffer (FIFO) has an equal size 4k
deep, and each buffer can be addressed at an offset 0x0 + n*0x1000, where n
i buffer number n (0 to 15), but only one buffer can be accessed at one
time, i.e. 188 bytes must be written to one buffer before you can address
and write to another buffer. Buffer management can be either handled by
polling buffer status flags (empty, almost full) or handled by the hardware
generating an interrupt each time a buffer is nearly empty, or when there is
room for 1880 bytes.
The user (or client) of the RM will be a number of processes using the write
() POSIX API.
The scenario as I se it is as follows:
One RM process can handle all communication with the card, i.e. the process
can contain the interrupt service routine, and have a thread started each
time a new write message from the user appears.
One RM process for each buffer, i.e. 16 processes will handle the
communication with the card. In addition an 17th process will contain the
interrupt service routine and low level configuration functions for the
card. Since one buffer can be addressed at one time, synchronisation must be
used between the processes, maybe using the mutex functionality offered by
What is the best way of doing this?
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