PCI interrupt sharing and interrupt latency- summary

I am posting an account of what I have learned about this issue in the last few days in case
this helps someone in the future. I have posted this in a new thread so that the subject
line will be more descriptive of the issue (see ‘Long interrupt latency caused by ethernet driver’
thread for how this started). This applies to machines with PCI architectures.

I originally noticed a very long interrupt latency (1 msec) on my a/d converter interrupt.
The cause was that the a/d converter shared it’s interrupt with
the onboard ethernet. The solution is to make sure a real-time device
doesn’t share its interrupt. (By the way, I never encountered this on the ISA bus, because
its interrupts weren’t shared).

However, I have found that this solution (not sharing interrupts) is not easy to realize. On
some motherboards the PCI slot’s interrupt line (INTA#) is electrically shared with motherboard
devices, and there is no way around this. My Dell machine has a setup screen that allows one to
assign the IRQs of PCI devices. This machine has the 850 chipset, which has the capability to route
8
interrupts from slots and onboard devices to IRQ lines (so some of the slots shouldn’t have to
electrically
share). But no matter which slot I place the card in it always winds up sharing its interrupt with
some motherboard device. I dont know if this is a BIOS limitation or if Dell really wired
this motherboard so that all slot interrupts are electrically shared with something. The only fix I
could
see was to put the a/d card in the slot that causes its interrupt to be shared with the
onboard USB controller (I dont use the USB).

What to do about this is unclear. My only conclusion is to be careful in selecting PCI bus machines
so that one has some provision in the setup screens for influencing interrupt routing.


Art Hays
National Institutes of Health
avhays@nih.gov

I think this falls into the category of “For any given real-time
application both the software (O/S and application code) and the hardware
must be capable of meeting the required deadlines”. The “classic” example
on x86 is SMM/SMI.

Art Hays wrote:

What to do about this is unclear. My only conclusion is to be careful in
selecting PCI bus machines
so that one has some provision in the setup screens for influencing
interrupt routing.


Art Hays
National Institutes of Health
avhays@nih.gov