make again

Every time I think I have make figured out I come across a new thing that I
can’t quite do. Here’s my latest. The line in question is the very last
line Assuming the following portion of a make file:

BIN := /some/silly/long/path
OBJ := /some/path
SOURCE1 := $(wildcard *.c)
SOURCE2 := $(wildcard *.cc)
SOURCE3 := $(wildcard *.cpp)
SOURCE4 := $(wildcard *.C)
PROGS := $(foreach FILE, $(SOURCES), $(basename $(FILE) ) )
OBJS := $(foreach FILE, $(PROGS), $OBJ/$(FILE).o )
XPROGS := foreach FILE, $(PROGS), $(BIN)/$(FILE) )

$(XPROGS) : $(BIN)/% : $(OBJ)/%.o
@sh -c “usemsg -c $@ $.[Cc]

What I want is to execute the usemsg with the proper source file. I was not
able to come up with a make command that did the trick so I tried a shell
construct. It works BUT if the source file is opened by an editor, for
instance, the shell picks up the temp file too.

How can I get just the correct entry from the $(SOURCES) macro?