Makefiles and compilation dependencies

Hi,

I have a question for those out doing complex builds (anything non-trivial).

How are you handling dependencies in your Makefiles for your .h files so that when one changes it re-compiles all the corresponding source code.

It’s trivial to set up rules for handling .c and .cpp files correctly but I am hoping to set up a painless .h rule.

I was looking at doing:

-Wp,-MD to use the -MD feature of gcc (using 3.3.1) but when I added this to my CFLAGS line it doesn’t appear to do anything. Yes, I see the -Wp,-MD on the compile line but once a source file is compiled if I go and do a touch *.h where *.h is included by my .c/.cpp file and run make again it says everything is up to date.

So it doesn’t appear that -MD gets passed to the pre-processor of gcc or else 3.3.1 isn’t supporting that feature.

That means doing something else. The question is what’s the next best option. Looking for ideas here ideally with an example.

TIA,

Tim

I never could get the gcc stuff working ( I didn’t try hard though). I use makedepend to create a dependency file that the makefile include.

Mario,

Did you download this from the 3rd party package someplace?

When I do a ‘MakeDepend’ or ‘makedepend’ from the command line I get a command not found. Doing a find on MakeD* or maked* turns up nothing.

I really hate using makedepend since it’s fraught with errors when handling #ifdef directives in include files which is why I was hoping the gcc option worked.

Tim

I am using g++ -M to process my source files and output everything to a depend file, which I “include” in the makefile.
The dependencies are computed properly (as I can see when I take a look at the generated depend file), but make recompiles everything all the time as if it was totally ignoring the include depend file statement.
Here is the makefile

SRCDIR = src
OBJDIR = obj
BINDIR = bin
vpath %.cc $(SRCDIR) $(SRCDIR)/test $(SRCDIR)/aux $(SRCDIR)/physicalDevices $(SRCDIR)/utils

CC = g++
CFLAGS =
INCLUDE = -I/usr/include -Iinclude

depend: makedirs
@echo “” > $(OBJDIR)/Makefile.dep
@find $(SRCDIR) -name ".cc" | xargs $(CC) $(CFLAGS) $(INCLUDE) -M | sed 's|^([^.].o)|$(OBJDIR)/\1|’ >> $(OBJDIR)/Makefile.dep
@sed -e ‘s|^$(SRCDIR)/test|$(OBJDIR)|’ -e ‘s|^$(SRCDIR)/aux|$(OBJDIR)|’ -e ‘s|^$(SRCDIR)/physicalDevices|$(OBJDIR)|’ -e ‘s|^$(SRCDIR)/utils|$(OBJDIR)|’ -e ‘s|^$(SRCDIR)|$(OBJDIR)|’ < $(OBJDIR)/Makefile.dep > $(OBJDIR)/Makefile.dep.dep
@mv $(OBJDIR)/Makefile.dep.dep $(OBJDIR)/Makefile.dep
@echo dependency file $(OBJDIR)/Makefile.dep generated

-include $(OBJDIR)/Makefile.dep

Any chance the date/time on your source files is newer than the current time on your machine so that it always thinks the files should be compilied?

Assuming that’s not the case, can you show some of the output from the makedepend file. Also what does the actual compilation line in your Makefile(s) look like that uses the makedepend file.

Tim

Yes that was the problem. When transferring files between different machines I get problems with time info. I now touch all my files after transferring them from another machine.
Thaks

I switched from g++ to QCC (isn’t it the same?) and I get a lot of error generating the dependency file with QCC -M
A lot of warnings about undefined references to this and that…
The funny thing is that it compiles fine.

So now I am generating my dependencies with g++ and compiling with QCC. I need to compile with QCC because I am having problems generating shared libraries with g++ (see another thread about that).