AMD64 and i86e (I think that’s how Intel calls their 64 bit implementation).
But it’s hard to see that supported in the near future under QNX >
Are you referring to the Athlon64 ? IIRC it has a 32 bit code address, 64 bit
data address, and a 64 bit word size. If I am right, then pointers to data
should still be equal to the size of an integer (address size == word size)
(although a pointer to a function would be a different size than an int).
I’m just curious, does it mean Athlon64 has Harvard architecture, or
they just limited code segment to be in lower half of memory?
Eduard.
The basic point is that I said Alain is safe in what he is doing (in the
context that he was doing it - he was asking about a very specific piece of
code that he supplied). I still stand by the statement it should work
reliably in the given context (i.e. QNX 6.2.1 gcc 2.95).
AMD64 and i86e (I think that’s how Intel calls their 64 bit
implementation).
But it’s hard to see that supported in the near future under QNX >
Are you referring to the Athlon64 ? IIRC it has a 32 bit code address, 64
bit
data address, and a 64 bit word size.
No C complier implement int as 32 bit and pointer as 64 bits.
If I am right, then pointers to data
should still be equal to the size of an integer (address size == word
size)
(although a pointer to a function would be a different size than an int).
The basic point is that I said Alain is safe in what he is doing (in the
context that he was doing it - he was asking about a very specific piece
of
code that he supplied). I still stand by the statement it should work
reliably in the given context (i.e. QNX 6.2.1 gcc 2.95).
AMD64 and i86e (I think that’s how Intel calls their 64 bit
implementation).
But it’s hard to see that supported in the near future under QNX >
Are you referring to the Athlon64 ? IIRC it has a 32 bit code address,
64 bit
data address, and a 64 bit word size. If I am right, then pointers to
data
should still be equal to the size of an integer (address size == word
size)
(although a pointer to a function would be a different size than an
int).
I’m just curious, does it mean Athlon64 has Harvard architecture, or
they just limited code segment to be in lower half of memory?
All adresses are expressed as 64 bit, and virtual address space can be 64
bit wide.
However physical access to memory is 52 bit.
Eduard.
The basic point is that I said Alain is safe in what he is doing (in the
context that he was doing it - he was asking about a very specific piece
of
code that he supplied). I still stand by the statement it should work
reliably in the given context (i.e. QNX 6.2.1 gcc 2.95).
