PCI bus master

We have developed a PC/104+ board with the PLX9054 bus master.

The call:
h->hdev = pci_attach_device( NULL, PCI_INIT_ALL, cardnr, &h->pci );

is successful, but when I examine ‘h->pci.BaseAddressSize_’, I find there
are no address regions are allocated.

But if I do a PCI configuration register dump, the base address registers
are as follows:
0x0010: 0xfebbff00
0x0014: 0x0000e801
0x0018: 0xfea00000
0x001c: 0xfe900000
0x0020: 0x00000000
0x0024: 0x00000000

The output of pci -vv is:
Class = Bridge (Unknown)
Vendor ID = 10b5h, PLX Technology
Device ID = 9054h, PCI 9054 PCI I/O Accelerator
PCI index = 0h
Class Codes = 068000h
Revision ID = ch
Bus number = 0
Device number = 9
Function num = 0
Status Reg = 290h
Command Reg = 117h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 40h
Cache Line Size= 8h un-cacheable
Subsystem Vendor ID = 10b5h
Subsystem ID = 9054h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = 0h
Capabilities Pointer = 40h
Capability ID = 1h
Capabilities = 1h - 0h
Capability ID = 6h
Capabilities = 80h - 3h
Capability ID = 3h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 01 48 01 00 00 00 00 00 06 4c 80 00 03 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

I have another application where a PC/104+ target PCI device is used, but
there the operation works perfectly using the exact code.

Why does QNX not pick up the memory spaces in the bus master device?

Francois_

Francois Joubert wrote:

We have developed a PC/104+ board with the PLX9054 bus master.

Why is the ‘Class’ of your device a bridge?

AFAIK … the PCI space of a bridge device has a different structure.

Regards

Armin




The call:
h->hdev = pci_attach_device( NULL, PCI_INIT_ALL, cardnr, &h->pci );

is successful, but when I examine 'h->pci.BaseAddressSize> ', I find there
are no address regions are allocated.

But if I do a PCI configuration register dump, the base address registers
are as follows:
0x0010: 0xfebbff00
0x0014: 0x0000e801
0x0018: 0xfea00000
0x001c: 0xfe900000
0x0020: 0x00000000
0x0024: 0x00000000

The output of pci -vv is:
Class = Bridge (Unknown)
Vendor ID = 10b5h, PLX Technology
Device ID = 9054h, PCI 9054 PCI I/O Accelerator
PCI index = 0h
Class Codes = 068000h
Revision ID = ch
Bus number = 0
Device number = 9
Function num = 0
Status Reg = 290h
Command Reg = 117h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 40h
Cache Line Size= 8h un-cacheable
Subsystem Vendor ID = 10b5h
Subsystem ID = 9054h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = 0h
Capabilities Pointer = 40h
Capability ID = 1h
Capabilities = 1h - 0h
Capability ID = 6h
Capabilities = 80h - 3h
Capability ID = 3h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 01 48 01 00 00 00 00 00 06 4c 80 00 03 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

I have another application where a PC/104+ target PCI device is used, but
there the operation works perfectly using the exact code.

Why does QNX not pick up the memory spaces in the bus master device?

Francois

These are the default power-on values of the PCI9054 device. It can however
be changed by configuring the on-board EEPROM or a local bus access.

The PCI configuration space has a header type of 0 therefore not the header
type of a bridge (header type 1).

Francois

“Armin Steinhoff” <a-steinhoff@web.de> wrote in message
news:ceq8t2$b0r$1@inn.qnx.com

Francois Joubert wrote:
We have developed a PC/104+ board with the PLX9054 bus master.

Why is the ‘Class’ of your device a bridge?

AFAIK … the PCI space of a bridge device has a different structure.

Regards

Armin





The call:
h->hdev = pci_attach_device( NULL, PCI_INIT_ALL, cardnr, &h->pci );

is successful, but when I examine 'h->pci.BaseAddressSize> ', I find
there
are no address regions are allocated.

But if I do a PCI configuration register dump, the base address
registers
are as follows:
0x0010: 0xfebbff00
0x0014: 0x0000e801
0x0018: 0xfea00000
0x001c: 0xfe900000
0x0020: 0x00000000
0x0024: 0x00000000

The output of pci -vv is:
Class = Bridge (Unknown)
Vendor ID = 10b5h, PLX Technology
Device ID = 9054h, PCI 9054 PCI I/O Accelerator
PCI index = 0h
Class Codes = 068000h
Revision ID = ch
Bus number = 0
Device number = 9
Function num = 0
Status Reg = 290h
Command Reg = 117h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 40h
Cache Line Size= 8h un-cacheable
Subsystem Vendor ID = 10b5h
Subsystem ID = 9054h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = 0h
Capabilities Pointer = 40h
Capability ID = 1h
Capabilities = 1h - 0h
Capability ID = 6h
Capabilities = 80h - 3h
Capability ID = 3h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 01 48 01 00 00 00 00 00 06 4c 80 00 03 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

I have another application where a PC/104+ target PCI device is used,
but
there the operation works perfectly using the exact code.

Why does QNX not pick up the memory spaces in the bus master device?

Francois

We don’t support attaching to bridge type devices. This is due to the fact
that non-x86 platforms don’t have a BIOS to setup the bridges. You will have
to use pci_read/write routines to setup your bridge.

“Francois Joubert” <francois@truvelo.co.za> wrote in message
news:cepujq$2f5$1@inn.qnx.com

We have developed a PC/104+ board with the PLX9054 bus master.

The call:
h->hdev = pci_attach_device( NULL, PCI_INIT_ALL, cardnr, &h->pci );

is successful, but when I examine 'h->pci.BaseAddressSize> ', I find
there
are no address regions are allocated.

But if I do a PCI configuration register dump, the base address registers
are as follows:
0x0010: 0xfebbff00
0x0014: 0x0000e801
0x0018: 0xfea00000
0x001c: 0xfe900000
0x0020: 0x00000000
0x0024: 0x00000000

The output of pci -vv is:
Class = Bridge (Unknown)
Vendor ID = 10b5h, PLX Technology
Device ID = 9054h, PCI 9054 PCI I/O Accelerator
PCI index = 0h
Class Codes = 068000h
Revision ID = ch
Bus number = 0
Device number = 9
Function num = 0
Status Reg = 290h
Command Reg = 117h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 40h
Cache Line Size= 8h un-cacheable
Subsystem Vendor ID = 10b5h
Subsystem ID = 9054h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = 0h
Capabilities Pointer = 40h
Capability ID = 1h
Capabilities = 1h - 0h
Capability ID = 6h
Capabilities = 80h - 3h
Capability ID = 3h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 01 48 01 00 00 00 00 00 06 4c 80 00 03 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

I have another application where a PC/104+ target PCI device is used, but
there the operation works perfectly using the exact code.

Why does QNX not pick up the memory spaces in the bus master device?

Francois

Ok, but the header type of our device is 0, therefore pci_attach_device can
PCI_INIT_ALL.

“Hugh Brown” <hsbrown@qnx.com> wrote in message
news:ceqgrf$gjo$1@inn.qnx.com

We don’t support attaching to bridge type devices. This is due to the fact
that non-x86 platforms don’t have a BIOS to setup the bridges. You will
have
to use pci_read/write routines to setup your bridge.

“Francois Joubert” <> francois@truvelo.co.za> > wrote in message
news:cepujq$2f5$> 1@inn.qnx.com> …
We have developed a PC/104+ board with the PLX9054 bus master.

The call:
h->hdev = pci_attach_device( NULL, PCI_INIT_ALL, cardnr, &h->pci );

is successful, but when I examine 'h->pci.BaseAddressSize> ', I find
there
are no address regions are allocated.

But if I do a PCI configuration register dump, the base address
registers
are as follows:
0x0010: 0xfebbff00
0x0014: 0x0000e801
0x0018: 0xfea00000
0x001c: 0xfe900000
0x0020: 0x00000000
0x0024: 0x00000000

The output of pci -vv is:
Class = Bridge (Unknown)
Vendor ID = 10b5h, PLX Technology
Device ID = 9054h, PCI 9054 PCI I/O Accelerator
PCI index = 0h
Class Codes = 068000h
Revision ID = ch
Bus number = 0
Device number = 9
Function num = 0
Status Reg = 290h
Command Reg = 117h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 40h
Cache Line Size= 8h un-cacheable
Subsystem Vendor ID = 10b5h
Subsystem ID = 9054h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = 0h
Capabilities Pointer = 40h
Capability ID = 1h
Capabilities = 1h - 0h
Capability ID = 6h
Capabilities = 80h - 3h
Capability ID = 3h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 01 48 01 00 00 00 00 00 06 4c 80 00 03 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

I have another application where a PC/104+ target PCI device is used,
but
there the operation works perfectly using the exact code.

Why does QNX not pick up the memory spaces in the bus master device?

Francois

\

We look at the device class and if it is a bridge type device, with the
exception of CardBus bridges, we leave them alone.

“Francois Joubert” <francois@truvelo.co.za> wrote in message
news:ceqp45$mcg$1@inn.qnx.com

Ok, but the header type of our device is 0, therefore pci_attach_device
can
PCI_INIT_ALL.

“Hugh Brown” <> hsbrown@qnx.com> > wrote in message
news:ceqgrf$gjo$> 1@inn.qnx.com> …
We don’t support attaching to bridge type devices. This is due to the
fact
that non-x86 platforms don’t have a BIOS to setup the bridges. You will
have
to use pci_read/write routines to setup your bridge.

“Francois Joubert” <> francois@truvelo.co.za> > wrote in message
news:cepujq$2f5$> 1@inn.qnx.com> …
We have developed a PC/104+ board with the PLX9054 bus master.

The call:
h->hdev = pci_attach_device( NULL, PCI_INIT_ALL, cardnr, &h->pci );

is successful, but when I examine 'h->pci.BaseAddressSize> ', I find
there
are no address regions are allocated.

But if I do a PCI configuration register dump, the base address
registers
are as follows:
0x0010: 0xfebbff00
0x0014: 0x0000e801
0x0018: 0xfea00000
0x001c: 0xfe900000
0x0020: 0x00000000
0x0024: 0x00000000

The output of pci -vv is:
Class = Bridge (Unknown)
Vendor ID = 10b5h, PLX Technology
Device ID = 9054h, PCI 9054 PCI I/O Accelerator
PCI index = 0h
Class Codes = 068000h
Revision ID = ch
Bus number = 0
Device number = 9
Function num = 0
Status Reg = 290h
Command Reg = 117h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 40h
Cache Line Size= 8h un-cacheable
Subsystem Vendor ID = 10b5h
Subsystem ID = 9054h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = 0h
Capabilities Pointer = 40h
Capability ID = 1h
Capabilities = 1h - 0h
Capability ID = 6h
Capabilities = 80h - 3h
Capability ID = 3h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 01 48 01 00 00 00 00 00 06 4c 80 00 03 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

I have another application where a PC/104+ target PCI device is used,
but
there the operation works perfectly using the exact code.

Why does QNX not pick up the memory spaces in the bus master device?

Francois



\

Well, don’t be shy Hugh. You don’t leave them alone - you leave them
half-initialized. Function returns early with success, but leaves half of
the fields uninitialized. Right? Or do I have to quote the source code line?

The fix for x86 actually takes 2 lines of code, which QNX refused to do
despite my loud screaming.
I can actually post a fixed binary if anyone wants it. Standard discalimers
apply…

– igor

“Hugh Brown” <hsbrown@qnx.com> wrote in message
news:cer9jm$52r$1@inn.qnx.com

We look at the device class and if it is a bridge type device, with the
exception of CardBus bridges, we leave them alone.

“Francois Joubert” <> francois@truvelo.co.za> > wrote in message
news:ceqp45$mcg$> 1@inn.qnx.com> …
Ok, but the header type of our device is 0, therefore pci_attach_device
can
PCI_INIT_ALL.

“Hugh Brown” <> hsbrown@qnx.com> > wrote in message
news:ceqgrf$gjo$> 1@inn.qnx.com> …
We don’t support attaching to bridge type devices. This is due to the
fact
that non-x86 platforms don’t have a BIOS to setup the bridges. You
will
have
to use pci_read/write routines to setup your bridge.

“Francois Joubert” <> francois@truvelo.co.za> > wrote in message
news:cepujq$2f5$> 1@inn.qnx.com> …
We have developed a PC/104+ board with the PLX9054 bus master.

The call:
h->hdev = pci_attach_device( NULL, PCI_INIT_ALL, cardnr, &h->pci );

is successful, but when I examine 'h->pci.BaseAddressSize> ', I
find
there
are no address regions are allocated.

But if I do a PCI configuration register dump, the base address
registers
are as follows:
0x0010: 0xfebbff00
0x0014: 0x0000e801
0x0018: 0xfea00000
0x001c: 0xfe900000
0x0020: 0x00000000
0x0024: 0x00000000

The output of pci -vv is:
Class = Bridge (Unknown)
Vendor ID = 10b5h, PLX Technology
Device ID = 9054h, PCI 9054 PCI I/O Accelerator
PCI index = 0h
Class Codes = 068000h
Revision ID = ch
Bus number = 0
Device number = 9
Function num = 0
Status Reg = 290h
Command Reg = 117h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 40h
Cache Line Size= 8h un-cacheable
Subsystem Vendor ID = 10b5h
Subsystem ID = 9054h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = 0h
Capabilities Pointer = 40h
Capability ID = 1h
Capabilities = 1h - 0h
Capability ID = 6h
Capabilities = 80h - 3h
Capability ID = 3h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 01 48 01 00 00 00 00 00 06 4c 80 00 03 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

I have another application where a PC/104+ target PCI device is
used,
but
there the operation works perfectly using the exact code.

Why does QNX not pick up the memory spaces in the bus master device?

Francois





\

On the PCI9054 device one can change the class code via the serial EEPROM,
but the header type never change.
If I were QNX, I will look at the header type and then decide to leave it
alone.

“Igor Kovalenko” <kovalenko@comcast.net> wrote in message
news:ces9u6$q6n$1@inn.qnx.com

Well, don’t be shy Hugh. You don’t leave them alone - you leave them
half-initialized. Function returns early with success, but leaves half
of
the fields uninitialized. Right? Or do I have to quote the source code
line?

The fix for x86 actually takes 2 lines of code, which QNX refused to do
despite my loud screaming.
I can actually post a fixed binary if anyone wants it. Standard
discalimers
apply…

– igor

“Hugh Brown” <> hsbrown@qnx.com> > wrote in message
news:cer9jm$52r$> 1@inn.qnx.com> …
We look at the device class and if it is a bridge type device, with the
exception of CardBus bridges, we leave them alone.

“Francois Joubert” <> francois@truvelo.co.za> > wrote in message
news:ceqp45$mcg$> 1@inn.qnx.com> …
Ok, but the header type of our device is 0, therefore
pci_attach_device
can
PCI_INIT_ALL.

“Hugh Brown” <> hsbrown@qnx.com> > wrote in message
news:ceqgrf$gjo$> 1@inn.qnx.com> …
We don’t support attaching to bridge type devices. This is due to
the
fact
that non-x86 platforms don’t have a BIOS to setup the bridges. You
will
have
to use pci_read/write routines to setup your bridge.

“Francois Joubert” <> francois@truvelo.co.za> > wrote in message
news:cepujq$2f5$> 1@inn.qnx.com> …
We have developed a PC/104+ board with the PLX9054 bus master.

The call:
h->hdev = pci_attach_device( NULL, PCI_INIT_ALL, cardnr,
&h->pci );

is successful, but when I examine 'h->pci.BaseAddressSize> ', I
find
there
are no address regions are allocated.

But if I do a PCI configuration register dump, the base address
registers
are as follows:
0x0010: 0xfebbff00
0x0014: 0x0000e801
0x0018: 0xfea00000
0x001c: 0xfe900000
0x0020: 0x00000000
0x0024: 0x00000000

The output of pci -vv is:
Class = Bridge (Unknown)
Vendor ID = 10b5h, PLX Technology
Device ID = 9054h, PCI 9054 PCI I/O Accelerator
PCI index = 0h
Class Codes = 068000h
Revision ID = ch
Bus number = 0
Device number = 9
Function num = 0
Status Reg = 290h
Command Reg = 117h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 40h
Cache Line Size= 8h un-cacheable
Subsystem Vendor ID = 10b5h
Subsystem ID = 9054h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = 0h
Capabilities Pointer = 40h
Capability ID = 1h
Capabilities = 1h - 0h
Capability ID = 6h
Capabilities = 80h - 3h
Capability ID = 3h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 01 48 01 00 00 00 00 00 06 4c 80 00 03 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

I have another application where a PC/104+ target PCI device is
used,
but
there the operation works perfectly using the exact code.

Why does QNX not pick up the memory spaces in the bus master
device?

Francois







\

The funniest part is that non-transparent bridges don’t really require any
esoteric setup. They by definition imply presense of another bus with its
own local ‘host’ (CPU) and that CPU will initialize the bridge by some
device-dependent code in the EEPROM … So to the host (main) they look much
like a dumb PCI device - you only need to do the usual stuff like querying
and filling BARs, etc.

Bottom line is, all the argument about not supporting those bridges seems
rather bogus to me… but what do I know :wink:

“Francois Joubert” <francois@truvelo.co.za> wrote in message
news:cesg0k$1ab$1@inn.qnx.com

On the PCI9054 device one can change the class code via the serial EEPROM,
but the header type never change.
If I were QNX, I will look at the header type and then decide to leave it
alone.

“Igor Kovalenko” <> kovalenko@comcast.net> > wrote in message
news:ces9u6$q6n$> 1@inn.qnx.com> …
Well, don’t be shy Hugh. You don’t leave them alone - you leave them
half-initialized. Function returns early with success, but leaves half
of
the fields uninitialized. Right? Or do I have to quote the source code
line?

The fix for x86 actually takes 2 lines of code, which QNX refused to
do
despite my loud screaming.
I can actually post a fixed binary if anyone wants it. Standard
discalimers
apply…

– igor

“Hugh Brown” <> hsbrown@qnx.com> > wrote in message
news:cer9jm$52r$> 1@inn.qnx.com> …
We look at the device class and if it is a bridge type device, with
the
exception of CardBus bridges, we leave them alone.

“Francois Joubert” <> francois@truvelo.co.za> > wrote in message
news:ceqp45$mcg$> 1@inn.qnx.com> …
Ok, but the header type of our device is 0, therefore
pci_attach_device
can
PCI_INIT_ALL.

“Hugh Brown” <> hsbrown@qnx.com> > wrote in message
news:ceqgrf$gjo$> 1@inn.qnx.com> …
We don’t support attaching to bridge type devices. This is due to
the
fact
that non-x86 platforms don’t have a BIOS to setup the bridges. You
will
have
to use pci_read/write routines to setup your bridge.

“Francois Joubert” <> francois@truvelo.co.za> > wrote in message
news:cepujq$2f5$> 1@inn.qnx.com> …
We have developed a PC/104+ board with the PLX9054 bus master.

The call:
h->hdev = pci_attach_device( NULL, PCI_INIT_ALL, cardnr,
&h->pci );

is successful, but when I examine 'h->pci.BaseAddressSize> ', I
find
there
are no address regions are allocated.

But if I do a PCI configuration register dump, the base address
registers
are as follows:
0x0010: 0xfebbff00
0x0014: 0x0000e801
0x0018: 0xfea00000
0x001c: 0xfe900000
0x0020: 0x00000000
0x0024: 0x00000000

The output of pci -vv is:
Class = Bridge (Unknown)
Vendor ID = 10b5h, PLX Technology
Device ID = 9054h, PCI 9054 PCI I/O Accelerator
PCI index = 0h
Class Codes = 068000h
Revision ID = ch
Bus number = 0
Device number = 9
Function num = 0
Status Reg = 290h
Command Reg = 117h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents
enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 40h
Cache Line Size= 8h un-cacheable
Subsystem Vendor ID = 10b5h
Subsystem ID = 9054h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = 0h
Capabilities Pointer = 40h
Capability ID = 1h
Capabilities = 1h - 0h
Capability ID = 6h
Capabilities = 80h - 3h
Capability ID = 3h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 01 48 01 00 00 00 00 00 06 4c 80 00 03 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

I have another application where a PC/104+ target PCI device is
used,
but
there the operation works perfectly using the exact code.

Why does QNX not pick up the memory spaces in the bus master
device?

Francois









\

Hi Igor,

in the moment I have the same “Bridge (Unknown)” trouble.

Is there a way to get your ‘fixed binary’ ?
Is there a bug fix from QSSL available ?

The target hardware is a board with a QSPAN PCI interface which was
supported by the PCI primitives of QNX4.
Hope there is a way to support it under QNX6.3 …

Best Regards

Armin Steinhoff



Igor Kovalenko wrote:

Well, don’t be shy Hugh. You don’t leave them alone - you leave them
half-initialized. Function returns early with success, but leaves half of
the fields uninitialized. Right? Or do I have to quote the source code line?

The fix for x86 actually takes 2 lines of code, which QNX refused to do
despite my loud screaming.
I can actually post a fixed binary if anyone wants it. Standard discalimers
apply…

– igor

“Hugh Brown” <> hsbrown@qnx.com> > wrote in message
news:cer9jm$52r$> 1@inn.qnx.com> …

We look at the device class and if it is a bridge type device, with the
exception of CardBus bridges, we leave them alone.

“Francois Joubert” <> francois@truvelo.co.za> > wrote in message
news:ceqp45$mcg$> 1@inn.qnx.com> …

Ok, but the header type of our device is 0, therefore pci_attach_device

can

PCI_INIT_ALL.

“Hugh Brown” <> hsbrown@qnx.com> > wrote in message
news:ceqgrf$gjo$> 1@inn.qnx.com> …

We don’t support attaching to bridge type devices. This is due to the

fact

that non-x86 platforms don’t have a BIOS to setup the bridges. You

will

have

to use pci_read/write routines to setup your bridge.

“Francois Joubert” <> francois@truvelo.co.za> > wrote in message
news:cepujq$2f5$> 1@inn.qnx.com> …

We have developed a PC/104+ board with the PLX9054 bus master.

The call:
h->hdev = pci_attach_device( NULL, PCI_INIT_ALL, cardnr, &h->pci );

is successful, but when I examine 'h->pci.BaseAddressSize> ', I

find

there

are no address regions are allocated.

But if I do a PCI configuration register dump, the base address

registers

are as follows:
0x0010: 0xfebbff00
0x0014: 0x0000e801
0x0018: 0xfea00000
0x001c: 0xfe900000
0x0020: 0x00000000
0x0024: 0x00000000

The output of pci -vv is:
Class = Bridge (Unknown)
Vendor ID = 10b5h, PLX Technology
Device ID = 9054h, PCI 9054 PCI I/O Accelerator
PCI index = 0h
Class Codes = 068000h
Revision ID = ch
Bus number = 0
Device number = 9
Function num = 0
Status Reg = 290h
Command Reg = 117h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 40h
Cache Line Size= 8h un-cacheable
Subsystem Vendor ID = 10b5h
Subsystem ID = 9054h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = 0h
Capabilities Pointer = 40h
Capability ID = 1h
Capabilities = 1h - 0h
Capability ID = 6h
Capabilities = 80h - 3h
Capability ID = 3h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 01 48 01 00 00 00 00 00 06 4c 80 00 03 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

I have another application where a PC/104+ target PCI device is

used,

but

there the operation works perfectly using the exact code.

Why does QNX not pick up the memory spaces in the bus master device?

Francois





\

“Armin Steinhoff” <a-steinhoff@web.de> wrote in message
news:cjgpap$7hh$1@inn.qnx.com

Hugh Brown wrote:
We look at the device class and if it is a bridge type device, with the
exception of CardBus bridges, we leave them alone.

Will the attach_device call return the a valid handle ??

Depends on what you consider a ‘valid’ handle. Suppose you wrote a function
that allocates a structure, initializes it and returns you the address. Now
imagine your function in some cases does not really initialize half of that
structure, but still returns the address. Do you call that a ‘valid’ handle?

I call it a bogus handle.

Is the device then attached ??

If you bought a car, but it is missing half of the engine parts, have you
really bought a car? Yeah, technically the car is yours. You just can’t
drive it…

Regards

Armin Steinhoff




“Francois Joubert” <> francois@truvelo.co.za> > wrote in message
news:ceqp45$mcg$> 1@inn.qnx.com> …

Ok, but the header type of our device is 0, therefore pci_attach_device

can

PCI_INIT_ALL.

“Hugh Brown” <> hsbrown@qnx.com> > wrote in message
news:ceqgrf$gjo$> 1@inn.qnx.com> …

We don’t support attaching to bridge type devices. This is due to the

fact

that non-x86 platforms don’t have a BIOS to setup the bridges. You will

have

to use pci_read/write routines to setup your bridge.

“Francois Joubert” <> francois@truvelo.co.za> > wrote in message
news:cepujq$2f5$> 1@inn.qnx.com> …

We have developed a PC/104+ board with the PLX9054 bus master.

The call:
h->hdev = pci_attach_device( NULL, PCI_INIT_ALL, cardnr, &h->pci );

is successful, but when I examine 'h->pci.BaseAddressSize> ', I find

there

are no address regions are allocated.

But if I do a PCI configuration register dump, the base address

registers

are as follows:
0x0010: 0xfebbff00
0x0014: 0x0000e801
0x0018: 0xfea00000
0x001c: 0xfe900000
0x0020: 0x00000000
0x0024: 0x00000000

The output of pci -vv is:
Class = Bridge (Unknown)
Vendor ID = 10b5h, PLX Technology
Device ID = 9054h, PCI 9054 PCI I/O Accelerator
PCI index = 0h
Class Codes = 068000h
Revision ID = ch
Bus number = 0
Device number = 9
Function num = 0
Status Reg = 290h
Command Reg = 117h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 40h
Cache Line Size= 8h un-cacheable
Subsystem Vendor ID = 10b5h
Subsystem ID = 9054h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = 0h
Capabilities Pointer = 40h
Capability ID = 1h
Capabilities = 1h - 0h
Capability ID = 6h
Capabilities = 80h - 3h
Capability ID = 3h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 01 48 01 00 00 00 00 00 06 4c 80 00 03 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

I have another application where a PC/104+ target PCI device is used,

but

there the operation works perfectly using the exact code.

Why does QNX not pick up the memory spaces in the bus master device?

Francois




\

Hugh Brown wrote:

We look at the device class and if it is a bridge type device, with the
exception of CardBus bridges, we leave them alone.

Will the attach_device call return the a valid handle ??
Is the device then attached ??

Regards

Armin Steinhoff




“Francois Joubert” <> francois@truvelo.co.za> > wrote in message
news:ceqp45$mcg$> 1@inn.qnx.com> …

Ok, but the header type of our device is 0, therefore pci_attach_device

can

PCI_INIT_ALL.

“Hugh Brown” <> hsbrown@qnx.com> > wrote in message
news:ceqgrf$gjo$> 1@inn.qnx.com> …

We don’t support attaching to bridge type devices. This is due to the

fact

that non-x86 platforms don’t have a BIOS to setup the bridges. You will

have

to use pci_read/write routines to setup your bridge.

“Francois Joubert” <> francois@truvelo.co.za> > wrote in message
news:cepujq$2f5$> 1@inn.qnx.com> …

We have developed a PC/104+ board with the PLX9054 bus master.

The call:
h->hdev = pci_attach_device( NULL, PCI_INIT_ALL, cardnr, &h->pci );

is successful, but when I examine 'h->pci.BaseAddressSize> ', I find

there

are no address regions are allocated.

But if I do a PCI configuration register dump, the base address

registers

are as follows:
0x0010: 0xfebbff00
0x0014: 0x0000e801
0x0018: 0xfea00000
0x001c: 0xfe900000
0x0020: 0x00000000
0x0024: 0x00000000

The output of pci -vv is:
Class = Bridge (Unknown)
Vendor ID = 10b5h, PLX Technology
Device ID = 9054h, PCI 9054 PCI I/O Accelerator
PCI index = 0h
Class Codes = 068000h
Revision ID = ch
Bus number = 0
Device number = 9
Function num = 0
Status Reg = 290h
Command Reg = 117h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 40h
Cache Line Size= 8h un-cacheable
Subsystem Vendor ID = 10b5h
Subsystem ID = 9054h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = 0h
Capabilities Pointer = 40h
Capability ID = 1h
Capabilities = 1h - 0h
Capability ID = 6h
Capabilities = 80h - 3h
Capability ID = 3h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 01 48 01 00 00 00 00 00 06 4c 80 00 03 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

I have another application where a PC/104+ target PCI device is used,

but

there the operation works perfectly using the exact code.

Why does QNX not pick up the memory spaces in the bus master device?

Francois




\

“Armin Steinhoff” <a-steinhoff@web.de> wrote in message
news:cjf788$1j7$1@inn.qnx.com

Hi Igor,

in the moment I have the same “Bridge (Unknown)” trouble.

Is there a way to get your ‘fixed binary’ ?

It is attached, along with a little test program.
Kill the standard pci-bios server and run this one. Then run 'pcitest ’ with values of your QSPAN (from pci -v). If you
run the program with old and new pci-bios, you should see the difference.

Here is how it looks for me (Intel 21554 non-transparent PCI-PCI bridge):

With standard pci-bios server (notice empty subsystem IDs, memory ranges and
bogus IRQ).

bsc_01.NILE# ./pcitest 0x1011 0x46
Dump of pci_dev_info…
46 00 11 10 00 00 00 00 02 50 01 00 00 00 00 00
00 80 06 00 FF 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

pci_dev_info structure…
DeviceId: 46
VendorId: 1011
SubsystemId: 0
SubsystemVendorId: 0
BusNumber: 2
DevFunc: 10:0
Revision: 1
Rsvd[5]: 0 0 0 0 0
Class: 68000
Irq: 255
CpuIoTranslation: 0
CpuMemTranslation: 0
CpuIsaTranslation: 0
CpuBmstrTranslation: 0
PciBaseAddress[6]: 0 0 0 0 0 0
CpuBaseAddress[6]: 0 0 0 0 0 0
BaseAddressSize: 0 0 0 0 0 0
PciRom: 0
CpuRom: 0
RomSize: 0
Rsvd1[3]: 0 0 0

With new pci-bios server:

bsc_01.NILE# slay -f pci-bios; ./pci-bios &
[1] 549310471
bsc_01.NILE#
bsc_01.NILE# ./pcitest 0x1011 0x46
Dump of pci_dev_info…
46 00 11 10 02 01 CE 11 02 50 01 00 00 00 00 00
00 80 06 00 0C 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 14 F4 00 00 00 00
01 24 00 00 00 00 00 00 00 34 14 F4 00 00 00 00
00 00 00 EE 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 14 F4 00 00 00 00
01 24 00 00 00 00 00 00 00 34 14 F4 00 00 00 00
00 00 00 EE 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 10 00 00 00 01 00 00
00 01 00 00 00 00 00 02 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

pci_dev_info structure…
DeviceId: 46
VendorId: 1011
SubsystemId: 102
SubsystemVendorId: 11ce
BusNumber: 2
DevFunc: 10:0
Revision: 1
Rsvd[5]: 0 0 0 0 0
Class: 68000
Irq: 12
CpuIoTranslation: 0
CpuMemTranslation: 0
CpuIsaTranslation: 0
CpuBmstrTranslation: 0
PciBaseAddress[6]: f4140000 2401 f4143400 ee000000 0 0
CpuBaseAddress[6]: f4140000 2401 f4143400 ee000000 0 0
BaseAddressSize: 1000 100 100 2000000 0 0
PciRom: 0
CpuRom: 0
RomSize: 0
Rsvd1[3]: 0 0 0
bsc_01.NILE#

Is there a bug fix from QSSL available ?

There’s no generally released fix. If you have support contract, you may be
able to get it from your TAM.

The target hardware is a board with a QSPAN PCI interface which was
supported by the PCI primitives of QNX4.
Hope there is a way to support it under QNX6.3 …

The attached pci-bios is based on 6.2.1. I don’t have it for 6.3 right now.
I think it will work just fine, but as usual - use at your own risk.

Regards
– igor

Best Regards

Armin Steinhoff



Igor Kovalenko wrote:
Well, don’t be shy Hugh. You don’t leave them alone - you leave them
half-initialized. Function returns early with success, but leaves half
of
the fields uninitialized. Right? Or do I have to quote the source code
line?

The fix for x86 actually takes 2 lines of code, which QNX refused to
do
despite my loud screaming.
I can actually post a fixed binary if anyone wants it. Standard
discalimers
apply…

– igor

“Hugh Brown” <> hsbrown@qnx.com> > wrote in message
news:cer9jm$52r$> 1@inn.qnx.com> …

We look at the device class and if it is a bridge type device, with the
exception of CardBus bridges, we leave them alone.

“Francois Joubert” <> francois@truvelo.co.za> > wrote in message
news:ceqp45$mcg$> 1@inn.qnx.com> …

Ok, but the header type of our device is 0, therefore pci_attach_device

can

PCI_INIT_ALL.

“Hugh Brown” <> hsbrown@qnx.com> > wrote in message
news:ceqgrf$gjo$> 1@inn.qnx.com> …

We don’t support attaching to bridge type devices. This is due to the

fact

that non-x86 platforms don’t have a BIOS to setup the bridges. You

will

have

to use pci_read/write routines to setup your bridge.

“Francois Joubert” <> francois@truvelo.co.za> > wrote in message
news:cepujq$2f5$> 1@inn.qnx.com> …

We have developed a PC/104+ board with the PLX9054 bus master.

The call:
h->hdev = pci_attach_device( NULL, PCI_INIT_ALL, cardnr, &h->pci );

is successful, but when I examine 'h->pci.BaseAddressSize> ', I

find

there

are no address regions are allocated.

But if I do a PCI configuration register dump, the base address

registers

are as follows:
0x0010: 0xfebbff00
0x0014: 0x0000e801
0x0018: 0xfea00000
0x001c: 0xfe900000
0x0020: 0x00000000
0x0024: 0x00000000

The output of pci -vv is:
Class = Bridge (Unknown)
Vendor ID = 10b5h, PLX Technology
Device ID = 9054h, PCI 9054 PCI I/O Accelerator
PCI index = 0h
Class Codes = 068000h
Revision ID = ch
Bus number = 0
Device number = 9
Function num = 0
Status Reg = 290h
Command Reg = 117h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 40h
Cache Line Size= 8h un-cacheable
Subsystem Vendor ID = 10b5h
Subsystem ID = 9054h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = 0h
Capabilities Pointer = 40h
Capability ID = 1h
Capabilities = 1h - 0h
Capability ID = 6h
Capabilities = 80h - 3h
Capability ID = 3h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 01 48 01 00 00 00 00 00 06 4c 80 00 03 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

I have another application where a PC/104+ target PCI device is

used,

but

there the operation works perfectly using the exact code.

Why does QNX not pick up the memory spaces in the bus master device?

Francois






\

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M8G5S("5D("T@9&5V9G5N8R E> M8V(@0G5S("5X("T@1&5V9FX@)7@@+2!D=V]R9" E> !B=7,@)60@:6]S=&%R M=" E;&QX("T@:6]E;F0@)6QL>
M````````8G5S(“5D(&UE;7-T87)T(“5L;’@@+2!M96UE;F0@)6QL> M`````````````````````````````````&)U<R E9"!P<F5F<W1A<G0@)6QL M>" M('!R969E;F0@)6QL> !297-E<G9E($E/(&9A:6QE9 !297-E<G9E($U% M32!F86EL960``````````````````````````````%)E<V5R=F4@4DU%32!F M86EL960@+2!3=&%R=" E;&QX("T@16YD("5L;'@`0G5S(&YO="!F;W5N9"$` M!T8B!”=7,@)7@@+2!$979F;B E>” M(&1W;W)D(“5X&1E=B!I<R!. M54Q,(0``````````````````````````56YA8FQE('1O('-E960@<F5S;W5R M8V4@061D<B E;&QX("T@4VEZ92 E> ```/__``````````#_____`````%)A M;F=E(&-H96-K(&9A:6QE9" H24\I("T@1&5V("5X("T@5F5N9" E>" M($-L M87-S("5X("T@061D<B E>" M(%-I>F4@)6QL> !)3R E>" E;&QX$%L;&]C
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M("T@061D<B E;&QX(“T@4VEZ92 E;&QX'!R968``$U%32 E;&QX("5L;'@@ M)7,```````````````````````````````````!286YG92!C:&5C:R!F86EL M960@*%)/32D@+2!$978@)7@@+2!696YD("5X("T@0VQA<W,@)7@@+2!!9&1R M("5X("T@4VEZ92 E;&QX%)/32 E>” M("5L;’@24\@)6QL>" E;&QX$U%
M32 E;&QX("5L;’@`4D]-(“5L;’@@)6QL> M````````````<V-A;E]D979I8V4@0G5S("5D("T@1&5V:6-E("5D("T@1G5N M8W1I;VX@)60%9E;F1O”!$979I8V4@
M)7@@26YD97@@)60@0VQA

Igor Kovalenko wrote:

“Armin Steinhoff” <> a-steinhoff@web.de> > wrote in message
news:cjf788$1j7$> 1@inn.qnx.com> …

Hi Igor,

in the moment I have the same “Bridge (Unknown)” trouble.

Is there a way to get your ‘fixed binary’ ?


It is attached, along with a little test program.

Thank you very much!

Regards

Armin

Kill the standard pci-bios server and run this one. Then run 'pcitest ’ with values of your QSPAN (from pci -v). If you
run the program with old and new pci-bios, you should see the difference.

Here is how it looks for me (Intel 21554 non-transparent PCI-PCI bridge):

With standard pci-bios server (notice empty subsystem IDs, memory ranges and
bogus IRQ).

bsc_01.NILE# ./pcitest 0x1011 0x46
Dump of pci_dev_info…
46 00 11 10 00 00 00 00 02 50 01 00 00 00 00 00
00 80 06 00 FF 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

pci_dev_info structure…
DeviceId: 46
VendorId: 1011
SubsystemId: 0
SubsystemVendorId: 0
BusNumber: 2
DevFunc: 10:0
Revision: 1
Rsvd[5]: 0 0 0 0 0
Class: 68000
Irq: 255
CpuIoTranslation: 0
CpuMemTranslation: 0
CpuIsaTranslation: 0
CpuBmstrTranslation: 0
PciBaseAddress[6]: 0 0 0 0 0 0
CpuBaseAddress[6]: 0 0 0 0 0 0
BaseAddressSize: 0 0 0 0 0 0
PciRom: 0
CpuRom: 0
RomSize: 0
Rsvd1[3]: 0 0 0

With new pci-bios server:

bsc_01.NILE# slay -f pci-bios; ./pci-bios &
[1] 549310471
bsc_01.NILE#
bsc_01.NILE# ./pcitest 0x1011 0x46
Dump of pci_dev_info…
46 00 11 10 02 01 CE 11 02 50 01 00 00 00 00 00
00 80 06 00 0C 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 14 F4 00 00 00 00
01 24 00 00 00 00 00 00 00 34 14 F4 00 00 00 00
00 00 00 EE 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 14 F4 00 00 00 00
01 24 00 00 00 00 00 00 00 34 14 F4 00 00 00 00
00 00 00 EE 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 10 00 00 00 01 00 00
00 01 00 00 00 00 00 02 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

pci_dev_info structure…
DeviceId: 46
VendorId: 1011
SubsystemId: 102
SubsystemVendorId: 11ce
BusNumber: 2
DevFunc: 10:0
Revision: 1
Rsvd[5]: 0 0 0 0 0
Class: 68000
Irq: 12
CpuIoTranslation: 0
CpuMemTranslation: 0
CpuIsaTranslation: 0
CpuBmstrTranslation: 0
PciBaseAddress[6]: f4140000 2401 f4143400 ee000000 0 0
CpuBaseAddress[6]: f4140000 2401 f4143400 ee000000 0 0
BaseAddressSize: 1000 100 100 2000000 0 0
PciRom: 0
CpuRom: 0
RomSize: 0
Rsvd1[3]: 0 0 0
bsc_01.NILE#


Is there a bug fix from QSSL available ?


There’s no generally released fix. If you have support contract, you may be
able to get it from your TAM.


The target hardware is a board with a QSPAN PCI interface which was
supported by the PCI primitives of QNX4.
Hope there is a way to support it under QNX6.3 …


The attached pci-bios is based on 6.2.1. I don’t have it for 6.3 right now.
I think it will work just fine, but as usual - use at your own risk.

Regards
– igor


Best Regards

Armin Steinhoff



Igor Kovalenko wrote:

Well, don’t be shy Hugh. You don’t leave them alone - you leave them
half-initialized. Function returns early with success, but leaves half

of

the fields uninitialized. Right? Or do I have to quote the source code

line?

The fix for x86 actually takes 2 lines of code, which QNX refused to

do

despite my loud screaming.
I can actually post a fixed binary if anyone wants it. Standard

discalimers

apply…

– igor

“Hugh Brown” <> hsbrown@qnx.com> > wrote in message
news:cer9jm$52r$> 1@inn.qnx.com> …


We look at the device class and if it is a bridge type device, with the
exception of CardBus bridges, we leave them alone.

“Francois Joubert” <> francois@truvelo.co.za> > wrote in message
news:ceqp45$mcg$> 1@inn.qnx.com> …


Ok, but the header type of our device is 0, therefore pci_attach_device

can


PCI_INIT_ALL.

“Hugh Brown” <> hsbrown@qnx.com> > wrote in message
news:ceqgrf$gjo$> 1@inn.qnx.com> …


We don’t support attaching to bridge type devices. This is due to the

fact


that non-x86 platforms don’t have a BIOS to setup the bridges. You

will


have


to use pci_read/write routines to setup your bridge.

“Francois Joubert” <> francois@truvelo.co.za> > wrote in message
news:cepujq$2f5$> 1@inn.qnx.com> …


We have developed a PC/104+ board with the PLX9054 bus master.

The call:
h->hdev = pci_attach_device( NULL, PCI_INIT_ALL, cardnr, &h->pci );

is successful, but when I examine 'h->pci.BaseAddressSize> ', I

find


there


are no address regions are allocated.

But if I do a PCI configuration register dump, the base address

registers


are as follows:
0x0010: 0xfebbff00
0x0014: 0x0000e801
0x0018: 0xfea00000
0x001c: 0xfe900000
0x0020: 0x00000000
0x0024: 0x00000000

The output of pci -vv is:
Class = Bridge (Unknown)
Vendor ID = 10b5h, PLX Technology
Device ID = 9054h, PCI 9054 PCI I/O Accelerator
PCI index = 0h
Class Codes = 068000h
Revision ID = ch
Bus number = 0
Device number = 9
Function num = 0
Status Reg = 290h
Command Reg = 117h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 40h
Cache Line Size= 8h un-cacheable
Subsystem Vendor ID = 10b5h
Subsystem ID = 9054h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = 0h
Capabilities Pointer = 40h
Capability ID = 1h
Capabilities = 1h - 0h
Capability ID = 6h
Capabilities = 80h - 3h
Capability ID = 3h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 01 48 01 00 00 00 00 00 06 4c 80 00 03 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

I have another application where a PC/104+ target PCI device is

used,


but


there the operation works perfectly using the exact code.

Why does QNX not pick up the memory spaces in the bus master device?

Francois







#include <hw/pci.h
#include <hw/pci_devices.h
#include <stdio.h
#include <stdlib.h
#include <libgen.h

int main(int argc, char argv)
{
int pidx;
void
hdl;
int phdl;
struct pci_dev_info inf;

if (argc < 3) {
fprintf(stderr, “usage: %s VendorId DeviceId\n(use hex values)\n”, basename(argv[0]));
exit(-1);
}

/
Connect to the PCI server /
phdl = pci_attach( 0 );
if( phdl == -1 ) {
fprintf( stderr, “Unable to initialize PCI\n” );

return EXIT_FAILURE;
}

/
Initialize the pci_dev_info structure /
memset( &inf, 0, sizeof( inf ) );
pidx = 0;

sscanf(argv[1], “%hx”, &inf.VendorId);
sscanf(argv[2], “%hx”, &inf.DeviceId);

hdl = pci_attach_device( NULL, PCI_INIT_ALL, pidx, &inf );
if( hdl == NULL ) {
fprintf( stderr, “Unable to locate adapter\n” );
} else {
/
Do something to the adapter /
int i;

fprintf(stderr, “Dump of pci_dev_info…\n”);
for(i=0; i<sizeof(inf); i++) {
unsigned char byte = (char)(
(((char )&inf)+i));
fprintf(stderr, "%02X ", byte);
if ((i+1)%16 == 0) fprintf(stderr, “\n”);
}
fprintf(stderr, “\n”);

fprintf(stderr, “pci_dev_info structure…\n”);
fprintf(stderr, “DeviceId:\t\t %hx\n”, inf.DeviceId);
fprintf(stderr, “VendorId:\t\t %hx\n”, inf.VendorId);
fprintf(stderr, “SubsystemId:\t\t %hx\n”, inf.SubsystemId);
fprintf(stderr, “SubsystemVendorId:\t %hx\n”, inf.SubsystemVendorId);
fprintf(stderr, “BusNumber:\t\t %hhu\n”, inf.BusNumber);
fprintf(stderr, “DevFunc:\t\t %hhu:%hhu\n”, PCI_DEVNO(inf.DevFunc), PCI_FUNCNO(inf.DevFunc));
fprintf(stderr, “Revision:\t\t %hhx\n”, inf.Revision);
fprintf(stderr, "Rsvd[5]:\t\t ");
for(i=0; i<sizeof(inf.Rsvd)/sizeof(inf.Rsvd[0]); i++)
fprintf(stderr, "%hhx ", inf.Rsvd> );
fprintf(stderr, “\n”);
fprintf(stderr, “Class:\t\t\t %x\n”, inf.Class);
fprintf(stderr, “Irq:\t\t\t %d\n”, inf.Irq);

fprintf(stderr, “CpuIoTranslation:\t %llx\n”, inf.CpuIoTranslation);
fprintf(stderr, “CpuMemTranslation:\t %llx\n”, inf.CpuMemTranslation);
fprintf(stderr, “CpuIsaTranslation:\t %llx\n”, inf.CpuIsaTranslation);
fprintf(stderr, “CpuBmstrTranslation:\t %llx\n”, inf.CpuBmstrTranslation);
fprintf(stderr, "PciBaseAddress[6]:\t ");
for(i=0; i<sizeof(inf.PciBaseAddress)/sizeof(inf.PciBaseAddress[0]); i++)
fprintf(stderr, "%llx ", inf.PciBaseAddress> );
fprintf(stderr, “\n”);
fprintf(stderr, "CpuBaseAddress[6]:\t ");
for(i=0; i<sizeof(inf.CpuBaseAddress)/sizeof(inf.CpuBaseAddress[0]); i++)
fprintf(stderr, "%llx ", inf.CpuBaseAddress> );
fprintf(stderr, “\n”);
fprintf(stderr, "BaseAddressSize:\t ");
for(i=0; i<sizeof(inf.BaseAddressSize)/sizeof(inf.BaseAddressSize[0]); i++)
fprintf(stderr, "%x ", inf.BaseAddressSize> );
fprintf(stderr, “\n”);
fprintf(stderr, “PciRom:\t\t\t %llx\n”, inf.PciRom);
fprintf(stderr, “CpuRom:\t\t\t %llx\n”, inf.CpuRom);
fprintf(stderr, “RomSize:\t\t %x\n”, inf.RomSize);
fprintf(stderr, "Rsvd1[3]:\t\t ");
for(i=0; i<sizeof(inf.Rsvd1)/sizeof(inf.Rsvd1[0]); i++)
fprintf(stderr, "%x ", inf.Rsvd1> );
fprintf(stderr, “\n”);

pci_detach_device( hdl );
}

/
Disconnect from the PCI server */
pci_detach( phdl );

return EXIT_SUCCESS;
}

Igor Kovalenko wrote:

“Armin Steinhoff” <> a-steinhoff@web.de> > wrote in message
news:cjgpap$7hh$> 1@inn.qnx.com> …

Hugh Brown wrote:

We look at the device class and if it is a bridge type device, with the
exception of CardBus bridges, we leave them alone.

Will the attach_device call return the a valid handle ??


Depends on what you consider a ‘valid’ handle. Suppose you wrote a function
that allocates a structure, initializes it and returns you the address. Now
imagine your function in some cases does not really initialize half of that
structure, but still returns the address. Do you call that a ‘valid’ handle?

I call it a bogus handle.

Yes … it’s really curious. It seems that pci_attach_device returns a
valid handle even if the pci_dev_info structure has not been completely
filled out.

My workaround is to use pci_read_config in order to fill out the missing
information of the pci_dev_info structure.

So I cross my fingers that the returned handle is really valid now and
for the next releases.

Thanks

Armin





Is the device then attached ??



If you bought a car, but it is missing half of the engine parts, have you
really bought a car? Yeah, technically the car is yours. You just can’t
drive it…


Regards

Armin Steinhoff





“Francois Joubert” <> francois@truvelo.co.za> > wrote in message
news:ceqp45$mcg$> 1@inn.qnx.com> …


Ok, but the header type of our device is 0, therefore pci_attach_device

can


PCI_INIT_ALL.

“Hugh Brown” <> hsbrown@qnx.com> > wrote in message
news:ceqgrf$gjo$> 1@inn.qnx.com> …


We don’t support attaching to bridge type devices. This is due to the

fact


that non-x86 platforms don’t have a BIOS to setup the bridges. You will

have


to use pci_read/write routines to setup your bridge.

“Francois Joubert” <> francois@truvelo.co.za> > wrote in message
news:cepujq$2f5$> 1@inn.qnx.com> …


We have developed a PC/104+ board with the PLX9054 bus master.

The call:
h->hdev = pci_attach_device( NULL, PCI_INIT_ALL, cardnr, &h->pci );

is successful, but when I examine 'h->pci.BaseAddressSize> ', I find

there


are no address regions are allocated.

But if I do a PCI configuration register dump, the base address

registers


are as follows:
0x0010: 0xfebbff00
0x0014: 0x0000e801
0x0018: 0xfea00000
0x001c: 0xfe900000
0x0020: 0x00000000
0x0024: 0x00000000

The output of pci -vv is:
Class = Bridge (Unknown)
Vendor ID = 10b5h, PLX Technology
Device ID = 9054h, PCI 9054 PCI I/O Accelerator
PCI index = 0h
Class Codes = 068000h
Revision ID = ch
Bus number = 0
Device number = 9
Function num = 0
Status Reg = 290h
Command Reg = 117h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 40h
Cache Line Size= 8h un-cacheable
Subsystem Vendor ID = 10b5h
Subsystem ID = 9054h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = 0h
Capabilities Pointer = 40h
Capability ID = 1h
Capabilities = 1h - 0h
Capability ID = 6h
Capabilities = 80h - 3h
Capability ID = 3h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 01 48 01 00 00 00 00 00 06 4c 80 00 03 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

I have another application where a PC/104+ target PCI device is used,

but


there the operation works perfectly using the exact code.

Why does QNX not pick up the memory spaces in the bus master device?

Francois




\

Igor Kovalenkowrote:
“Armin Steinhoff” <> a-steinhoff@web.de> > wrote in message
news:cjf788$1j7$> 1@inn.qnx.com> …

Hi Igor,

in the moment I have the same “Bridge (Unknown)” trouble.

Is there a way to get your ‘fixed binary’ ?

It is attached, along with a little test program.

Kill the standard pci-bios server and run this one. Then run 'pcitest
’ with values of your QSPAN (from
pci -v). If you
run the program with old and new pci-bios, you should see the
difference.

Here is how it looks for me (Intel 21554 non-transparent PCI-PCI
bridge):

With standard pci-bios server (notice empty subsystem IDs, memory
ranges and
bogus IRQ).

bsc_01.NILE# ./pcitest 0x1011 0x46
Dump of pci_dev_info…
46 00 11 10 00 00 00 00 02 50 01 00 00 00 00 00
00 80 06 00 FF 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

pci_dev_info structure…
DeviceId: 46
VendorId: 1011
SubsystemId: 0
SubsystemVendorId: 0
BusNumber: 2
DevFunc: 10:0
Revision: 1
Rsvd[5]: 0 0 0 0 0
Class: 68000
Irq: 255
CpuIoTranslation: 0
CpuMemTranslation: 0
CpuIsaTranslation: 0
CpuBmstrTranslation: 0
PciBaseAddress[6]: 0 0 0 0 0 0
CpuBaseAddress[6]: 0 0 0 0 0 0
BaseAddressSize: 0 0 0 0 0 0
PciRom: 0
CpuRom: 0
RomSize: 0
Rsvd1[3]: 0 0 0

With new pci-bios server:

bsc_01.NILE# slay -f pci-bios; ./pci-bios &
[1] 549310471
bsc_01.NILE#
bsc_01.NILE# ./pcitest 0x1011 0x46
Dump of pci_dev_info…
46 00 11 10 02 01 CE 11 02 50 01 00 00 00 00 00
00 80 06 00 0C 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 14 F4 00 00 00 00
01 24 00 00 00 00 00 00 00 34 14 F4 00 00 00 00
00 00 00 EE 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 14 F4 00 00 00 00
01 24 00 00 00 00 00 00 00 34 14 F4 00 00 00 00
00 00 00 EE 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 10 00 00 00 01 00 00
00 01 00 00 00 00 00 02 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

pci_dev_info structure…
DeviceId: 46
VendorId: 1011
SubsystemId: 102
SubsystemVendorId: 11ce
BusNumber: 2
DevFunc: 10:0
Revision: 1
Rsvd[5]: 0 0 0 0 0
Class: 68000
Irq: 12
CpuIoTranslation: 0
CpuMemTranslation: 0
CpuIsaTranslation: 0
CpuBmstrTranslation: 0
PciBaseAddress[6]: f4140000 2401 f4143400 ee000000 0 0
CpuBaseAddress[6]: f4140000 2401 f4143400 ee000000 0 0
BaseAddressSize: 1000 100 100 2000000 0 0
PciRom: 0
CpuRom: 0
RomSize: 0
Rsvd1[3]: 0 0 0
bsc_01.NILE#

Is there a bug fix from QSSL available ?

There’s no generally released fix. If you have support contract, you

may be
able to get it from your TAM.

The target hardware is a board with a QSPAN PCI interface which was
supported by the PCI primitives of QNX4.
Hope there is a way to support it under QNX6.3 …

The attached pci-bios is based on 6.2.1. I don’t have it for 6.3 right

now.
I think it will work just fine, but as usual - use at your own risk.

Regards
– igor

Best Regards

Armin Steinhoff



Igor Kovalenko wrote:
Well, don’t be shy Hugh. You don’t leave them alone - you leave
them
half-initialized. Function returns early with success, but leaves
half
of
the fields uninitialized. Right? Or do I have to quote the source
code
line?

The fix for x86 actually takes 2 lines of code, which QNX refused
to
do
despite my loud screaming.
I can actually post a fixed binary if anyone wants it. Standard
discalimers
apply…

– igor

“Hugh Brown” <> hsbrown@qnx.com> > wrote in message
news:cer9jm$52r$> 1@inn.qnx.com> …

We look at the device class and if it is a bridge type device, with
the
exception of CardBus bridges, we leave them alone.

“Francois Joubert” <> francois@truvelo.co.za> > wrote in message
news:ceqp45$mcg$> 1@inn.qnx.com> …

Ok, but the header type of our device is 0, therefore
pci_attach_device

can

PCI_INIT_ALL.

“Hugh Brown” <> hsbrown@qnx.com> > wrote in message
news:ceqgrf$gjo$> 1@inn.qnx.com> …

We don’t support attaching to bridge type devices. This is due to
the

fact

that non-x86 platforms don’t have a BIOS to setup the bridges. You

will

have

to use pci_read/write routines to setup your bridge.

“Francois Joubert” <> francois@truvelo.co.za> > wrote in message
news:cepujq$2f5$> 1@inn.qnx.com> …

We have developed a PC/104+ board with the PLX9054 bus master.

The call:
h->hdev = pci_attach_device( NULL, PCI_INIT_ALL, cardnr,
&h->pci );

is successful, but when I examine ‘h->pci.BaseAddressSize’, I

find

there

are no address regions are allocated.

But if I do a PCI configuration register dump, the base address

registers

are as follows:
0x0010: 0xfebbff00
0x0014: 0x0000e801
0x0018: 0xfea00000
0x001c: 0xfe900000
0x0020: 0x00000000
0x0024: 0x00000000

The output of pci -vv is:
Class = Bridge (Unknown)
Vendor ID = 10b5h, PLX Technology
Device ID = 9054h, PCI 9054 PCI I/O Accelerator
PCI index = 0h
Class Codes = 068000h
Revision ID = ch
Bus number = 0
Device number = 9
Function num = 0
Status Reg = 290h
Command Reg = 117h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 40h
Cache Line Size= 8h un-cacheable
Subsystem Vendor ID = 10b5h
Subsystem ID = 9054h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = 0h
Capabilities Pointer = 40h
Capability ID = 1h
Capabilities = 1h - 0h
Capability ID = 6h
Capabilities = 80h - 3h
Capability ID = 3h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 01 48 01 00 00 00 00 00 06 4c 80 00 03 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

I have another application where a PC/104+ target PCI device is

used,

but

there the operation works perfectly using the exact code.

Why does QNX not pick up the memory spaces in the bus master
device?

Francois






\

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PCI CARD NOT ACCESSIBLE

We have developed PCI I/O card, it is accessible under windows but is
not
being accessed in QNX. The problem seems to be similar to the above
posts.

Please help me out.

Thanks,
Randeep

singh.randeep@gmail.com

the output of pci -vv is

Class = Bridge (Unknown)
Vendor ID = 10b5h, PLX Technology
Device ID = 9054h, PCI 9054 PCI I/O Accelerator
PCI index = 0h
Class Codes = 068000h
Revision ID = bh
Bus number = 1
Device number = 4
Function num = 0
Status Reg = 290h
Command Reg = 117h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 20h
Cache Line Size= 10h un-cacheable
Subsystem Vendor ID = 10b5h
Subsystem ID = 9054h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 10
CPU Interrupt = 0h
Capabilities Pointer = 40h
Capability ID = 1h
Capabilities = 1h - 0h
Capability ID = 6h
Capabilities = 80h - 3h
Capability ID = 3h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 01 48 01 00 00 00 00 00 06 4c 80 00 03 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

On 2006-02-20, randeep74 <singh.randeep@gmail-dot-com.no-spam.invalid> wrote:

PCI CARD NOT ACCESSIBLE

We have developed PCI I/O card, it is accessible under windows but is
not
being accessed in QNX. The problem seems to be similar to the above
posts.

Please help me out.

Thanks,
Randeep

singh.randeep@gmail.com

the output of pci -vv is

Class = Bridge (Unknown)
Vendor ID = 10b5h, PLX Technology
Device ID = 9054h, PCI 9054 PCI I/O Accelerator
PCI index = 0h
Class Codes = 068000h
Revision ID = bh
Bus number = 1
Device number = 4
Function num = 0
Status Reg = 290h
Command Reg = 117h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 20h
Cache Line Size= 10h un-cacheable
Subsystem Vendor ID = 10b5h
Subsystem ID = 9054h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 10
CPU Interrupt = 0h
Capabilities Pointer = 40h
Capability ID = 1h
Capabilities = 1h - 0h
Capability ID = 6h
Capabilities = 80h - 3h
Capability ID = 3h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 01 48 01 00 00 00 00 00 06 4c 80 00 03 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Change your Class code to something else. i.e., With my board that use
exactly the same PLX chip, I use 0e8000h instead of 068000h ". For some
reason, the QNX pci server cannot see the memory space and i/o space
when it have a “Bridge” class code.

Someone else on that newsgroup propose a patched version of pci-bios
that solve this problem, but never try it, I’ve already change the
Class code when I discovered it.

If you look my pci -vv output above, I have the same output than you,
but I have some “PCI Mem Address” and “PCI IO Address” that you don’t
have. I get those since I change the Class code…

Good luck.

Martin

=============================================================================
my “pci -vv” ouput:


Class = Intelligent I/O (Unknown)
Vendor ID = 10b5h, PLX Technology
Device ID = 9054h, PCI 9054 PCI I/O Accelerator
PCI index = 0h
Class Codes = 0e8000h
Revision ID = 0h
Bus number = 1
Device number = 12
Function num = 0
Status Reg = 290h
Command Reg = 7h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 20h
Cache Line Size= 8h un-cacheable
PCI Mem Address = e1130000h 32bit length 256 enabled
PCI IO Address = 9400h length 256 enabled
PCI Mem Address = e1120000h 32bit length 65536 enabled
PCI Mem Address = e1000000h 32bit length 1048576 enabled
Subsystem Vendor ID = 10b5h
Subsystem ID = 9054h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = bh
Capabilities Pointer = 40h
Capability ID = 1h
Capabilities = 1h - 0h
Capability ID = 6h
Capabilities = 80h - 3h
Capability ID = 3h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 01 48 01 00 00 00 00 00 06 4c 80 00 03 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00