On a modern x86 platform, is the interrupt controller running in
level-triggered or edge-triggered mode?
We’re assuming, especially since it’s PCI, that it should be in
level-triggered mode, but the system is behaving as if it’s in edge mode.
Is that possible?
Thanks,
lew
Hi Lewis,
PCI devices are level triggered
ISA are edge triggered
Your 8259 is capable of handling both, what sort of behaviour are you seeing?
Regards,
Erick.
Lewis Donzis <lew@perftech.com> wrote:
On a modern x86 platform, is the interrupt controller running in
level-triggered or edge-triggered mode?We’re assuming, especially since it’s PCI, that it should be in
level-triggered mode, but the system is behaving as if it’s in edge mode.
Is that possible?Thanks,
lew
Hi Lew,
I have recently wtitten small utility which tells exactly this
information, i.e. in which mode is every interrupt line. Are you running
QNX4 or QNX6? I have compilled it for both platforms.
Eduard.
In article <bumerc$6tv$2@inn.qnx.com>, lew@perftech.com says…
On a modern x86 platform, is the interrupt controller running in
level-triggered or edge-triggered mode?We’re assuming, especially since it’s PCI, that it should be in
level-triggered mode, but the system is behaving as if it’s in edge mode.
Is that possible?Thanks,
lew
The strange behavior is that a PCI card, which should be level triggered, is
acting as if it’s edge triggered…
We wake up in the interrupt code, do some work, unmask, and go back to
sleep, assuming that if the interrupt is still pending, we’ll wake right
back up again. We’ve been able to solve the problem by masking/unmasking
the interrupt on the card, thus forcing an edge on the interrupt line. but
it seems like this shouldn’t be necessary if the system is running in level
triggered mode. We assumed it must be level triggered since that’s normal
for PCI and you can’t share interrupts in edge triggered mode, but this
behavior is very strange.
The controller is a BGA part soldered on an off-the-shelf motherboard, so
it’s not easy to put a scope on the interrupt line coming out of the chip.
Anyway, we have a work-around, and the question seemed rather silly, but it
doesn’t hurt to ask!
Thanks,
lew
Erick Muis <emuis@node55.ott.qnx.com> wrote in message
news:bv66tr$sr3$1@inn.qnx.com…
Hi Lewis,
PCI devices are level triggered
ISA are edge triggeredYour 8259 is capable of handling both, what sort of behaviour are you
seeing?Regards,
Erick.
Lewis Donzis <> lew@perftech.com> > wrote:
On a modern x86 platform, is the interrupt controller running in
level-triggered or edge-triggered mode?We’re assuming, especially since it’s PCI, that it should be in
level-triggered mode, but the system is behaving as if it’s in edge
mode.
Is that possible?Thanks,
lew
\
Erick Muis
Hardware Group
QNX Software Systems Ltd.
Email: emuis at qnx.com
We’re on QNX6. Does this work by reading the 8259 registers? We’ve done
that and the results were as expected, i.e., when we’re not getting an
interrupt but the card says it’s interrupting, the 8259 says that the line
is inactive. But if your utility looks elsewhere, that might be
interesting.
Thanks,
lew
ed1k <nonexisting@invalid.domain> wrote in message
news:MPG.1a8b859bd2715de7989681@inn.qnx.com…
Hi Lew,
I have recently wtitten small utility which tells exactly this
information, i.e. in which mode is every interrupt line. Are you running
QNX4 or QNX6? I have compilled it for both platforms.Eduard.
In article <bumerc$6tv$> 2@inn.qnx.com> >, > lew@perftech.com > says…
On a modern x86 platform, is the interrupt controller running in
level-triggered or edge-triggered mode?We’re assuming, especially since it’s PCI, that it should be in
level-triggered mode, but the system is behaving as if it’s in edge
mode.
Is that possible?Thanks,
lew
In article <c02qi0$em3$1@inn.qnx.com>, lew@perftech.com says…
We’re on QNX6. Does this work by reading the 8259 registers?
It works by reading PIIX4 registers that are responsible to control
over the mode (level/edge) in which every interrupt line is. (There were
not such registers in old good time of 8259 chip). So, if you’re on QNX6,
and on x86 m/b with Intel chipset you can try
http://ed1k.qnx.org.ru/utils/picinfo/qnx6/picinfo.tgz
Eduard.
P.S. I don’t know details, but from my experience - every time when
system starts, only those interrupt lines are in level trigged mode which
corresponds to the PCI devices. So, if your board doesn’t fit to the PCI
standard (i.e. it has some incorrect info in PCI header), I think, it
could be a reason for incorrect PIC state.
We’ve done
that and the results were as expected, i.e., when we’re not getting an
interrupt but the card says it’s interrupting, the 8259 says that the line
is inactive. But if your utility looks elsewhere, that might be
interesting.Thanks,
lew
Interesting, thanks very much!
lew
In article <c1srht$sgc$1@inn.qnx.com>, lew@perftech.com says…
Interesting, thanks very much!
You’re welcome 
Did you find where the problem is?
Eduard.
lew
You’re welcome >
Eduard.
Yes, it appears that the Ethernet controller isn’t always interrupting when
it says it is! Toggling the mask in the card takes care of it.
Thanks,
lew
In article <c4as6c$c94$1@inn.qnx.com>, lew@perftech.com says…
Yes, it appears that the Ethernet controller isn’t always interrupting when
it says it is! Toggling the mask in the card takes care of it.
I have recently wrote SETIRQ utility. You can try it, or, at least,
“setirq -vvv list” can tell you much more than that “picinfo” one.
http://ed1k.qnx.org.ru/utils/setirq/qnx6/SETIRQ.TGZ
Eduard.
P.S. See more detailed announce in qnx.rtos newsgroup.
Thanks,
lew
Lewis Donzis wrote:
The strange behavior is that a PCI card, which should be level triggered, is
acting as if it’s edge triggered…We wake up in the interrupt code, do some work, unmask, and go back to
sleep,
Are you clearing the interrupt source on the card? This is necessary
for level sensitive operation.
Evan
Evan Hillas <evanh_at_@clear_dot_.net_dot_.nz> wrote in message
news:c60343$jlv$1@inn.qnx.com…
Are you clearing the interrupt source on the card? This is necessary
for level sensitive operation.
Yes, but in level mode, if you fail to clear the interrupt, then you should
just get another interrupt right away, and if you fail to ever clear it, it
usually hangs the machine. In our case, we were never getting another
interrupt, which is why it seemed more like edge mode.
Thanks,
lew