PCI Brigde configuration

Good afternoon,

I am trying to integrate a new card developed here. The card is
defined as a bridge (class = 068000). While the card is detected by
pci-bios and is shown using pci -vvv, I cannot access the card IO and
memory. I am able to configure the card using the pci_write_config32,
and the result of this configuration are reported by pci -vvv (see
result below).

I read that because this card is a bridge, I must use the
Configuration Address and Data Ports (addresses 0xCF8 and 0xCFC
respectively) using the Configuration mechanism #1 in order to access
IO and Memory on my card. This operation is supposed to handle
configuration transactions as Type 1 before passing them thru to my
card.

However, I have already verified that type 0 transactions can be
performed succesfully whether the Configuration Address and Data
Ports are accessed.

I also tried to program the primary and secondary buses (2 and 3
respectively) fields using the PCI-to-PCI bridge configuration
registers. The registers were programmed using pci_write_config32(),
however readbacks show that the registers were not programmed
(=zeros).

As a test I have succesfully attached (pci_attach_device()) the other
bridges (primary 0 and 1) and able to read their configuration
registers.

Lastly, the card class was changed (from 68000 to E8000) as I read
this suggestion in a previous posting. However, doing this, the card
is no longer detected by pci-bios.

My question is: along with locations 0xCF8 and 0xCFC, am I supposed to
program the other bridges (host to PCI, PCI to PCI) with values
indicating that the intension of accessing my card IO ports and
memory? If so, which registers? Once the access to the IO or memory
is completed, do I need to reprogram locations 0xCF8 and 0xCFC?

This is the result from pci -vvv before the pci_write_config32
operation

Class = Bridge (Unknown)
Vendor ID = 1895h, Unknown
Device ID = 1h, Unknown Unknown
PCI index = 0h
Class Codes = 068000h
Revision ID = 1h
Bus number = 2
Device number = 12
Function num = 0
Status Reg = 2b0h
Command Reg = 100h
I/O space access disabled
Memory space access disabled
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 42h
Cache Line Size= 10h un-cacheable
Max Lat = 26ns
Min Gnt = 8ns
PCI Int Pin = INT A
Interrupt line = no connection
Capabilities Pointer = 80h
Capability ID = 6h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00


This is the result from pci -vvv after the pci_write_config32
operation

Class = Bridge (Unknown)
Vendor ID = 1895h, Unknown
Device ID = 1h, Unknown Unknown
PCI index = 0h
Class Codes = 068000h
Revision ID = 1h
Bus number = 2
Device number = 12
Function num = 0
Status Reg = 2b0h
Command Reg = 143h
I/O space access enabled
Memory space access enabled
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping enabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 8h un-cacheable
Max Lat = 26ns
Min Gnt = 8ns
PCI Int Pin = INT A
Interrupt line = no connection
Capabilities Pointer = 80h
Capability ID = 6h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Thanks for your help.
Daniel

You don’t mention what version of the O/S you are using. Up to now we
haven’t evaluated bridge type “other”, but have added a command line option
to the PCI server to override this. The PCI server uses the 0xCF8 and 0xCFC
addresses for accessing configuration space, so you can just use the
standard pci_read and _write_config commands to access configuration space.

Please can you post the full pci -vv output from your machine, so that I can
take a look at it? PCI bridge type “other” don’t have secondary and
subordinate bus registers.

“dlabonte” <labonte_d@yahoo-dot-ca.no-spam.invalid> wrote in message
news:e09n8m$b16$1@inn.qnx.com

Good afternoon,

I am trying to integrate a new card developed here. The card is
defined as a bridge (class = 068000). While the card is detected by
pci-bios and is shown using pci -vvv, I cannot access the card IO and
memory. I am able to configure the card using the pci_write_config32,
and the result of this configuration are reported by pci -vvv (see
result below).

I read that because this card is a bridge, I must use the
Configuration Address and Data Ports (addresses 0xCF8 and 0xCFC
respectively) using the Configuration mechanism #1 in order to access
IO and Memory on my card. This operation is supposed to handle
configuration transactions as Type 1 before passing them thru to my
card.

However, I have already verified that type 0 transactions can be
performed succesfully whether the Configuration Address and Data
Ports are accessed.

I also tried to program the primary and secondary buses (2 and 3
respectively) fields using the PCI-to-PCI bridge configuration
registers. The registers were programmed using pci_write_config32(),
however readbacks show that the registers were not programmed
(=zeros).

As a test I have succesfully attached (pci_attach_device()) the other
bridges (primary 0 and 1) and able to read their configuration
registers.

Lastly, the card class was changed (from 68000 to E8000) as I read
this suggestion in a previous posting. However, doing this, the card
is no longer detected by pci-bios.

My question is: along with locations 0xCF8 and 0xCFC, am I supposed to
program the other bridges (host to PCI, PCI to PCI) with values
indicating that the intension of accessing my card IO ports and
memory? If so, which registers? Once the access to the IO or memory
is completed, do I need to reprogram locations 0xCF8 and 0xCFC?

This is the result from pci -vvv before the pci_write_config32
operation

Class = Bridge (Unknown)
Vendor ID = 1895h, Unknown
Device ID = 1h, Unknown Unknown
PCI index = 0h
Class Codes = 068000h
Revision ID = 1h
Bus number = 2
Device number = 12
Function num = 0
Status Reg = 2b0h
Command Reg = 100h
I/O space access disabled
Memory space access disabled
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 42h
Cache Line Size= 10h un-cacheable
Max Lat = 26ns
Min Gnt = 8ns
PCI Int Pin = INT A
Interrupt line = no connection
Capabilities Pointer = 80h
Capability ID = 6h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00


This is the result from pci -vvv after the pci_write_config32
operation

Class = Bridge (Unknown)
Vendor ID = 1895h, Unknown
Device ID = 1h, Unknown Unknown
PCI index = 0h
Class Codes = 068000h
Revision ID = 1h
Bus number = 2
Device number = 12
Function num = 0
Status Reg = 2b0h
Command Reg = 143h
I/O space access enabled
Memory space access enabled
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping enabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 8h un-cacheable
Max Lat = 26ns
Min Gnt = 8ns
PCI Int Pin = INT A
Interrupt line = no connection
Capabilities Pointer = 80h
Capability ID = 6h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Thanks for your help.
Daniel

I am using 6.3 with SP2 running on a Celeron M processor. The
configuration instructions include :

// Configure type 00 configuration Space Register
dwPciConfig = 0x08;
pci_write_config32( stBridge.BusNumber, stBridge.DevFunc, 0x0C, 1,
&dwPciConfig);

// Enable I/O and memory space, Parity Error Response, and System
Error Response
dwPciConfig = 0x143;
pci_write_config32( stBridge.BusNumber, stBridge.DevFunc, 0x04, 1,
&dwPciConfig);

// Primary bus number = 0x02; Secondary bus number = 0x03,
Subordinate bus number = 0x03
dwPciConfig = (0x02) | (0x03 << :sunglasses: | (0x03 << 16);
pci_write_config32( stBridge.BusNumber, stBridge.DevFunc, 0x18, 1,
&dwPciConfig);

The resulting listing from pci -vvv is

PCI version = 2.10

Class = Bridge (Host/PCI)
Vendor ID = 8086h, Intel Corporation
Device ID = 3580h,
PCI index = 0h
Class Codes = 060000h
Revision ID = 2h
Bus number = 0
Device number = 0
Function num = 0
Status Reg = 2090h
Command Reg = 106h
I/O space access disabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = NC
Interrupt line = 0
CPU Interrupt = 0h
Capabilities Pointer = 40h
Capability ID = 9h
Capabilities = 8105h - 0h
Device Dependent Registers:
0x40: 09 00 05 81 00 00 00 00 00 00 c1 fe 02 28 00 0e
0x50: 00 01 34 00 05 00 00 00 00 10 11 11 00 00 13 11
0x60: 0a 39 00 02 00 00 08 00 00 00 00 00 00 00 00 00
0x70: 02 09 00 00 54 60 00 02 00 00 00 00 00 00 00 00
0x80: 02 00 00 66 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 02 00 20 00 17 02 00 1f 01 00 00 00 00 00 00 00
0xB0: 00 00 f0 eb 00 00 00 00 00 00 00 00 20 10 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 08 00 00 00 00 00 02 00 09 01 00 00


Class = Display (VGA)
Vendor ID = 8086h, Intel Corporation
Device ID = 3582h, Unknown Unknown
PCI index = 0h
Class Codes = 030000h
Revision ID = 2h
Bus number = 0
Device number = 2
Function num = 0
Status Reg = 90h
Command Reg = 7h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
Header type = 0h Multi-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
PCI Mem Address = e8000000h prefetchable 32bit length 134217728
enabled
PCI Mem Address = e0000000h 32bit length 524288 enabled
PCI IO Address = 1800h length 8 enabled
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = bh
Capabilities Pointer = d0h
Capability ID = 1h
Capabilities = 221h - 0h
Device Dependent Registers:
0x40: 09 00 05 81 00 40 00 00 00 00 00 00 00 00 00 00
0x50: 00 01 34 00 05 00 00 00 00 00 02 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: ff a2 0a 30 00 00 00 00 e2 03 01 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 1e 4b 1c 00 13 02 72 02
0xC0: 07 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 01 00 21 02 00 00 00 00 08 c3 00 ff 25 00 00 00
0xE0: 2a 00 2b 00 98 00 ab 00 00 00 00 00 00 04 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00


Class = Display (Unknown)
Vendor ID = 8086h, Intel Corporation
Device ID = 3582h, Unknown Unknown
PCI index = 1h
Class Codes = 038000h
Revision ID = 2h
Bus number = 0
Device number = 2
Function num = 1
Status Reg = 90h
Command Reg = 7h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
Header type = 0h Multi-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
PCI Mem Address = f0000000h prefetchable 32bit length 134217728
enabled
PCI Mem Address = e0080000h 32bit length 524288 enabled
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = NC
Interrupt line = 0
Capabilities Pointer = d0h
Capability ID = 1h
Capabilities = 221h - 0h
Device Dependent Registers:
0x40: 09 00 05 81 00 40 00 00 00 00 00 00 00 00 00 00
0x50: 00 01 34 00 05 00 00 00 00 00 02 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: ff a2 0a 30 00 00 00 00 8a 04 01 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 a8 61 1c 00 67 d9 73 02
0xC0: 07 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 01 00 21 02 00 00 00 00 08 c3 00 ff 25 00 00 00
0xE0: 2a 00 2b 00 98 00 ab 00 00 00 00 00 00 04 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00


Class = Serial Bus (Universal Serial Bus)
Vendor ID = 8086h, Intel Corporation
Device ID = 24c2h, 82801DB USB UHCI Controller #1
PCI index = 0h
Class Codes = 0c0300h
Revision ID = 2h
Bus number = 0
Device number = 29
Function num = 0
Status Reg = 280h
Command Reg = 5h
I/O space access enabled
Memory space access disabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
Header type = 0h Multi-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
PCI IO Address = 1820h length 32 enabled
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = bh
Device Dependent Registers:
0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 3b 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00


Class = Serial Bus (Universal Serial Bus)
Vendor ID = 8086h, Intel Corporation
Device ID = 24c4h, 82801DB USB UHCI Controller #2
PCI index = 0h
Class Codes = 0c0300h
Revision ID = 2h
Bus number = 0
Device number = 29
Function num = 1
Status Reg = 280h
Command Reg = 5h
I/O space access enabled
Memory space access disabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
PCI IO Address = 1840h length 32 enabled
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT B
Interrupt line = 5
CPU Interrupt = 5h
Device Dependent Registers:
0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00


Class = Serial Bus (Universal Serial Bus)
Vendor ID = 8086h, Intel Corporation
Device ID = 24c7h, 82801DB USB UHCI Controller #3
PCI index = 0h
Class Codes = 0c0300h
Revision ID = 2h
Bus number = 0
Device number = 29
Function num = 2
Status Reg = 280h
Command Reg = 5h
I/O space access enabled
Memory space access disabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
PCI IO Address = 1860h length 32 enabled
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT C
Interrupt line = 5
CPU Interrupt = 5h
Device Dependent Registers:
0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00


Class = Serial Bus (Universal Serial Bus)
Vendor ID = 8086h, Intel Corporation
Device ID = 24cdh, 82801DB USB EHCI Controller
PCI index = 0h
Class Codes = 0c0320h
Revision ID = 2h
Bus number = 0
Device number = 29
Function num = 7
Status Reg = 290h
Command Reg = 106h
I/O space access disabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
PCI Mem Address = e0100000h 32bit length 1024 enabled
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT D
Interrupt line = 11
CPU Interrupt = bh
Capabilities Pointer = 50h
Capability ID = 1h
Capabilities = c9c2h - 0h
Capability ID = ah
Capabilities = 2080h - 0h
Device Dependent Registers:
0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 01 58 c2 c9 00 00 00 00 0a 00 80 20 00 00 00 00
0x60: 20 20 7f 00 00 00 00 00 01 00 00 00 00 00 0c c0
0x70: 00 00 d5 0f 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 78 bf 1f 00 88 83 00 00 60 0f 00 00 06 00 00 00


Class = Bridge (PCI/PCI)
Vendor ID = 8086h, Intel Corporation
Device ID = 244eh, 82801BA/CA/DB Hub Interface to PCI Bridge
PCI index = 0h
Class Codes = 060400h
Revision ID = 82h
Bus number = 0
Device number = 30
Function num = 0
Status Reg = 8080h
Command Reg = 107h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 1h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
Primary Bus Number = 0h
Secondary Bus Number = 1h
Subordinate Bus Number = 2h
Secondary Latency Timer = f8h
I/O Base = 20h
I/O Limit = 20h
Secondary Status = 2280h
Memory Base = e020h
Memory Limit = e030h
Prefetchable Memory Base = fff0h
Prefetchable Memory Limit= 0h
Prefetchable Base Upper 32 Bits = 0h
Prefetchable Limit Upper 32 Bits = 0h
I/O Base Upper 16 Bits = ffffh
I/O Limit Upper 16 Bits = ffffh
Bridge Control = 4h
PCI Int Pin = NC
Interrupt line = 0
CPU Interrupt = 0h
Device Dependent Registers:
0x40: 00 00 04 00 02 28 20 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 02 74 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 42 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 10 00 08 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 01 00 02 00 00 00 c0 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 60 0f 00 00


Class = Bridge (PCI/ISA)
Vendor ID = 8086h, Intel Corporation
Device ID = 24c0h, 82801DB LPC Interface Bridge
PCI index = 0h
Class Codes = 060100h
Revision ID = 2h
Bus number = 0
Device number = 31
Function num = 0
Status Reg = 280h
Command Reg = fh
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations monitor
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
Header type = 0h Multi-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = NC
Interrupt line = 0
CPU Interrupt = 0h
Device Dependent Registers:
0x40: 01 10 00 00 10 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 00 00 00 81 11 00 00 10 00 00 00
0x60: 0b 05 05 05 d0 00 00 00 05 80 0b 0b 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: ff fc 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 20 02 00 00 00 00 00 00 12 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 06 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 06 28 00 00 02 0f 00 00 04 00 00 00 00 00 00 00
0xE0: 10 00 00 ff 00 00 00 00 33 22 11 00 00 00 67 45
0xF0: 0f 00 40 00 00 00 00 00 60 0f 02 00 00 00 80 00


Class = Mass Storage (IDE)
Vendor ID = 8086h, Intel Corporation
Device ID = 24cbh, 82801DB IDE Controller (UltraATA/100)
PCI index = 0h
Class Codes = 01018ah
Revision ID = 2h
Bus number = 0
Device number = 31
Function num = 1
Status Reg = 280h
Command Reg = 7h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
PCI IO Address = 0h length 8 enabled
PCI IO Address = 0h length 4 enabled
PCI IO Address = 0h length 8 enabled
PCI IO Address = 0h length 4 enabled
PCI IO Address = 1810h length 16 enabled
PCI Mem Address = ffeffc00h 32bit length 1024 enabled
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = no connection
Device Dependent Registers:
0x40: 00 80 05 a3 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 04 00 00 00 00 00 00 00 00 00 00
0x60: 08 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00


Class = Serial Bus (SMBus)
Vendor ID = 8086h, Intel Corporation
Device ID = 24c3h, 82801DB SMBus Controller
PCI index = 0h
Class Codes = 0c0500h
Revision ID = 2h
Bus number = 0
Device number = 31
Function num = 3
Status Reg = 280h
Command Reg = 1h
I/O space access enabled
Memory space access disabled
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
PCI IO Address = 1880h length 32 enabled
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT B
Interrupt line = 5
CPU Interrupt = 5h
Device Dependent Registers:
0x40: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00


Class = Multimedia (Audio)
Vendor ID = 8086h, Intel Corporation
Device ID = 24c5h, 82801DB AC97 Audio Controller
PCI index = 0h
Class Codes = 040100h
Revision ID = 2h
Bus number = 0
Device number = 31
Function num = 5
Status Reg = 290h
Command Reg = 7h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
PCI IO Address = 1c00h length 256 enabled
PCI IO Address = 18c0h length 64 enabled
PCI Mem Address = e0100c00h 32bit length 512 enabled
PCI Mem Address = e0100800h 32bit length 256 enabled
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT B
Interrupt line = 5
CPU Interrupt = 5h
Capabilities Pointer = 50h
Capability ID = 1h
Capabilities = c9c2h - 0h
Device Dependent Registers:
0x40: 09 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 01 00 c2 c9 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00


Class = Network (Ethernet)
Vendor ID = 8086h, Intel Corporation
Device ID = 1078h, Unknown Unknown
PCI index = 0h
Class Codes = 020000h
Revision ID = 5h
Bus number = 1
Device number = 1
Function num = 0
Status Reg = 230h
Command Reg = 117h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 34h
Cache Line Size= 10h un-cacheable
PCI Mem Address = e0200000h 32bit length 131072 enabled
PCI IO Address = 2000h length 64 enabled
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 0ns
Min Gnt = 255ns
PCI Int Pin = INT A
Interrupt line = 5
CPU Interrupt = 5h
Capabilities Pointer = dch
Capability ID = 1h
Capabilities = 22h - 0h
Capability ID = 7h
Capabilities = 2h - 400000h
Device Dependent Registers:
0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 01 e4 22 00
0xE0: 00 00 00 00 07 00 02 00 00 00 40 00 00 00 00 00
0xF0: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00


Class = Bridge (PCI/PCI)
Vendor ID = 3388h, Hint Corp.
Device ID = 22h, Unknown Unknown
PCI index = 0h
Class Codes = 060400h
Revision ID = 4h
Bus number = 1
Device number = 4
Function num = 0
Status Reg = 2b0h
Command Reg = 107h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 1h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 21h
Cache Line Size= 10h un-cacheable
Primary Bus Number = 1h
Secondary Bus Number = 2h
Subordinate Bus Number = 2h
Secondary Latency Timer = fah
I/O Base = f1h
I/O Limit = 1h
Secondary Status = 2a0h
Memory Base = e030h
Memory Limit = e030h
Prefetchable Memory Base = fff1h
Prefetchable Memory Limit= 1h
Prefetchable Base Upper 32 Bits = 0h
Prefetchable Limit Upper 32 Bits = 0h
I/O Base Upper 16 Bits = ffffh
I/O Limit Upper 16 Bits = ffffh
Bridge Control = 4h
PCI Int Pin = NC
Interrupt line = 0
CPU Interrupt = 0h
Device Dependent Registers:
0x40: 00 00 04 00 00 00 00 02 00 00 10 00 10 10 10 10
0x50: 20 20 00 00 00 00 10 00 80 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 04 78 00 00 40 00 00
0x70: 01 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 01 e4 01 7e 00 00 00 00 06 e8 94 00 03 00 00 80
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00


Class = Network (Ethernet)
Vendor ID = 8086h, Intel Corporation
Device ID = 103ah, 82801DB LAN Controller with 82562ET/EZ (CNR)
PHY
PCI index = 0h
Class Codes = 020000h
Revision ID = 82h
Bus number = 1
Device number = 8
Function num = 0
Status Reg = 290h
Command Reg = 117h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 42h
Cache Line Size= 10h un-cacheable
PCI Mem Address = e0220000h 32bit length 4096 enabled
PCI IO Address = 2040h length 64 enabled
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 56ns
Min Gnt = 8ns
PCI Int Pin = INT A
Interrupt line = 5
CPU Interrupt = 5h
Capabilities Pointer = dch
Capability ID = 1h
Capabilities = fe22h - 3a004000h
Device Dependent Registers:
0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 22 fe
0xE0: 00 40 00 3a 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00


Class = Bridge (Unknown)
Vendor ID = 1895h, Unknown
Device ID = 1h, Unknown Unknown
PCI index = 0h
Class Codes = 068000h
Revision ID = 1h
Bus number = 2
Device number = 12
Function num = 0
Status Reg = 2b0h
Command Reg = 143h
I/O space access enabled
Memory space access enabled
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping enabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 8h un-cacheable
Max Lat = 26ns
Min Gnt = 8ns
PCI Int Pin = INT A
Interrupt line = 0
CPU Interrupt = 0h
Capabilities Pointer = 80h
Capability ID = 6h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00


Class = Multimedia (Unknown)
Vendor ID = 1131h, Philips Semiconductors
Device ID = 7146h, SAA7146 Multi Media Bridge Scaler
PCI index = 0h
Class Codes = 048000h
Revision ID = 1h
Bus number = 2
Device number = 15
Function num = 0
Status Reg = 280h
Command Reg = 202h
I/O space access disabled
Memory space access enabled
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 7bh
Cache Line Size= 0h
PCI Mem Address = e0300000h 32bit length 512 enabled
Subsystem Vendor ID = 18c9h
Subsystem ID = 2011h
Max Lat = 38ns
Min Gnt = 15ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = bh
Device Dependent Registers:
0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 80 00 00 00 80 00 00 00 80 00 00 00 80
0x90: 00 00 00 80 00 00 00 80 00 00 00 80 00 00 00 80
0xA0: 00 00 00 80 00 00 00 80 00 00 00 80 00 00 00 80
0xB0: 00 00 00 80 00 00 00 80 00 00 00 80 00 00 00 80
0xC0: 00 00 00 80 00 00 00 80 00 00 00 80 00 00 00 80
0xD0: 00 00 00 80 00 00 00 80 00 00 00 80 00 00 00 80
0xE0: 00 00 00 80 00 00 00 80 00 00 00 80 00 00 00 80
0xF0: 00 00 00 80 00 00 00 80 00 00 00 80 00 00 00 80

Daniel

Looking at your “pci -vv” output, I see that the I/O on the PCI-PCI bridge
on bus 1 device 4 is disabled, so you won’t be able to have any I/O
addresses on bus 2. If you look at the I/O Base and I/O Limit registers, you
will see that the base is 0xf1 and the limit is1, which means that I/O is
disabled. Ignore this if you are not using I/O on bus 2.
Also, any memory addresses that you will be using on bus 2 must be between
0xe0300000 and 0xe03fffff. You can program a memory address in this range
into your bridge type “other”.
Hope this helps.

“dlabonte” <labonte_d@yahoo-dot-ca.no-spam.invalid> wrote in message
news:e0btis$qdc$1@inn.qnx.com

I am using 6.3 with SP2 running on a Celeron M processor. The
configuration instructions include :

// Configure type 00 configuration Space Register
dwPciConfig = 0x08;
pci_write_config32( stBridge.BusNumber, stBridge.DevFunc, 0x0C, 1,
&dwPciConfig);

// Enable I/O and memory space, Parity Error Response, and System
Error Response
dwPciConfig = 0x143;
pci_write_config32( stBridge.BusNumber, stBridge.DevFunc, 0x04, 1,
&dwPciConfig);

// Primary bus number = 0x02; Secondary bus number = 0x03,
Subordinate bus number = 0x03
dwPciConfig = (0x02) | (0x03 << > :sunglasses: > | (0x03 << 16);
pci_write_config32( stBridge.BusNumber, stBridge.DevFunc, 0x18, 1,
&dwPciConfig);

The resulting listing from pci -vvv is

PCI version = 2.10

Class = Bridge (Host/PCI)
Vendor ID = 8086h, Intel Corporation
Device ID = 3580h,
PCI index = 0h
Class Codes = 060000h
Revision ID = 2h
Bus number = 0
Device number = 0
Function num = 0
Status Reg = 2090h
Command Reg = 106h
I/O space access disabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = NC
Interrupt line = 0
CPU Interrupt = 0h
Capabilities Pointer = 40h
Capability ID = 9h
Capabilities = 8105h - 0h
Device Dependent Registers:
0x40: 09 00 05 81 00 00 00 00 00 00 c1 fe 02 28 00 0e
0x50: 00 01 34 00 05 00 00 00 00 10 11 11 00 00 13 11
0x60: 0a 39 00 02 00 00 08 00 00 00 00 00 00 00 00 00
0x70: 02 09 00 00 54 60 00 02 00 00 00 00 00 00 00 00
0x80: 02 00 00 66 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 02 00 20 00 17 02 00 1f 01 00 00 00 00 00 00 00
0xB0: 00 00 f0 eb 00 00 00 00 00 00 00 00 20 10 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 08 00 00 00 00 00 02 00 09 01 00 00


Class = Display (VGA)
Vendor ID = 8086h, Intel Corporation
Device ID = 3582h, Unknown Unknown
PCI index = 0h
Class Codes = 030000h
Revision ID = 2h
Bus number = 0
Device number = 2
Function num = 0
Status Reg = 90h
Command Reg = 7h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
Header type = 0h Multi-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
PCI Mem Address = e8000000h prefetchable 32bit length 134217728
enabled
PCI Mem Address = e0000000h 32bit length 524288 enabled
PCI IO Address = 1800h length 8 enabled
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = bh
Capabilities Pointer = d0h
Capability ID = 1h
Capabilities = 221h - 0h
Device Dependent Registers:
0x40: 09 00 05 81 00 40 00 00 00 00 00 00 00 00 00 00
0x50: 00 01 34 00 05 00 00 00 00 00 02 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: ff a2 0a 30 00 00 00 00 e2 03 01 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 1e 4b 1c 00 13 02 72 02
0xC0: 07 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 01 00 21 02 00 00 00 00 08 c3 00 ff 25 00 00 00
0xE0: 2a 00 2b 00 98 00 ab 00 00 00 00 00 00 04 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00


Class = Display (Unknown)
Vendor ID = 8086h, Intel Corporation
Device ID = 3582h, Unknown Unknown
PCI index = 1h
Class Codes = 038000h
Revision ID = 2h
Bus number = 0
Device number = 2
Function num = 1
Status Reg = 90h
Command Reg = 7h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
Header type = 0h Multi-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
PCI Mem Address = f0000000h prefetchable 32bit length 134217728
enabled
PCI Mem Address = e0080000h 32bit length 524288 enabled
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = NC
Interrupt line = 0
Capabilities Pointer = d0h
Capability ID = 1h
Capabilities = 221h - 0h
Device Dependent Registers:
0x40: 09 00 05 81 00 40 00 00 00 00 00 00 00 00 00 00
0x50: 00 01 34 00 05 00 00 00 00 00 02 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: ff a2 0a 30 00 00 00 00 8a 04 01 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 a8 61 1c 00 67 d9 73 02
0xC0: 07 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 01 00 21 02 00 00 00 00 08 c3 00 ff 25 00 00 00
0xE0: 2a 00 2b 00 98 00 ab 00 00 00 00 00 00 04 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00


Class = Serial Bus (Universal Serial Bus)
Vendor ID = 8086h, Intel Corporation
Device ID = 24c2h, 82801DB USB UHCI Controller #1
PCI index = 0h
Class Codes = 0c0300h
Revision ID = 2h
Bus number = 0
Device number = 29
Function num = 0
Status Reg = 280h
Command Reg = 5h
I/O space access enabled
Memory space access disabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
Header type = 0h Multi-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
PCI IO Address = 1820h length 32 enabled
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = bh
Device Dependent Registers:
0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 3b 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00


Class = Serial Bus (Universal Serial Bus)
Vendor ID = 8086h, Intel Corporation
Device ID = 24c4h, 82801DB USB UHCI Controller #2
PCI index = 0h
Class Codes = 0c0300h
Revision ID = 2h
Bus number = 0
Device number = 29
Function num = 1
Status Reg = 280h
Command Reg = 5h
I/O space access enabled
Memory space access disabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
PCI IO Address = 1840h length 32 enabled
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT B
Interrupt line = 5
CPU Interrupt = 5h
Device Dependent Registers:
0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00


Class = Serial Bus (Universal Serial Bus)
Vendor ID = 8086h, Intel Corporation
Device ID = 24c7h, 82801DB USB UHCI Controller #3
PCI index = 0h
Class Codes = 0c0300h
Revision ID = 2h
Bus number = 0
Device number = 29
Function num = 2
Status Reg = 280h
Command Reg = 5h
I/O space access enabled
Memory space access disabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
PCI IO Address = 1860h length 32 enabled
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT C
Interrupt line = 5
CPU Interrupt = 5h
Device Dependent Registers:
0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00


Class = Serial Bus (Universal Serial Bus)
Vendor ID = 8086h, Intel Corporation
Device ID = 24cdh, 82801DB USB EHCI Controller
PCI index = 0h
Class Codes = 0c0320h
Revision ID = 2h
Bus number = 0
Device number = 29
Function num = 7
Status Reg = 290h
Command Reg = 106h
I/O space access disabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
PCI Mem Address = e0100000h 32bit length 1024 enabled
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT D
Interrupt line = 11
CPU Interrupt = bh
Capabilities Pointer = 50h
Capability ID = 1h
Capabilities = c9c2h - 0h
Capability ID = ah
Capabilities = 2080h - 0h
Device Dependent Registers:
0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 01 58 c2 c9 00 00 00 00 0a 00 80 20 00 00 00 00
0x60: 20 20 7f 00 00 00 00 00 01 00 00 00 00 00 0c c0
0x70: 00 00 d5 0f 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 78 bf 1f 00 88 83 00 00 60 0f 00 00 06 00 00 00


Class = Bridge (PCI/PCI)
Vendor ID = 8086h, Intel Corporation
Device ID = 244eh, 82801BA/CA/DB Hub Interface to PCI Bridge
PCI index = 0h
Class Codes = 060400h
Revision ID = 82h
Bus number = 0
Device number = 30
Function num = 0
Status Reg = 8080h
Command Reg = 107h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 1h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
Primary Bus Number = 0h
Secondary Bus Number = 1h
Subordinate Bus Number = 2h
Secondary Latency Timer = f8h
I/O Base = 20h
I/O Limit = 20h
Secondary Status = 2280h
Memory Base = e020h
Memory Limit = e030h
Prefetchable Memory Base = fff0h
Prefetchable Memory Limit= 0h
Prefetchable Base Upper 32 Bits = 0h
Prefetchable Limit Upper 32 Bits = 0h
I/O Base Upper 16 Bits = ffffh
I/O Limit Upper 16 Bits = ffffh
Bridge Control = 4h
PCI Int Pin = NC
Interrupt line = 0
CPU Interrupt = 0h
Device Dependent Registers:
0x40: 00 00 04 00 02 28 20 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 02 74 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 42 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 10 00 08 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 01 00 02 00 00 00 c0 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 60 0f 00 00


Class = Bridge (PCI/ISA)
Vendor ID = 8086h, Intel Corporation
Device ID = 24c0h, 82801DB LPC Interface Bridge
PCI index = 0h
Class Codes = 060100h
Revision ID = 2h
Bus number = 0
Device number = 31
Function num = 0
Status Reg = 280h
Command Reg = fh
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations monitor
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
Header type = 0h Multi-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = NC
Interrupt line = 0
CPU Interrupt = 0h
Device Dependent Registers:
0x40: 01 10 00 00 10 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 00 00 00 81 11 00 00 10 00 00 00
0x60: 0b 05 05 05 d0 00 00 00 05 80 0b 0b 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: ff fc 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 20 02 00 00 00 00 00 00 12 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 06 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 06 28 00 00 02 0f 00 00 04 00 00 00 00 00 00 00
0xE0: 10 00 00 ff 00 00 00 00 33 22 11 00 00 00 67 45
0xF0: 0f 00 40 00 00 00 00 00 60 0f 02 00 00 00 80 00


Class = Mass Storage (IDE)
Vendor ID = 8086h, Intel Corporation
Device ID = 24cbh, 82801DB IDE Controller (UltraATA/100)
PCI index = 0h
Class Codes = 01018ah
Revision ID = 2h
Bus number = 0
Device number = 31
Function num = 1
Status Reg = 280h
Command Reg = 7h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
PCI IO Address = 0h length 8 enabled
PCI IO Address = 0h length 4 enabled
PCI IO Address = 0h length 8 enabled
PCI IO Address = 0h length 4 enabled
PCI IO Address = 1810h length 16 enabled
PCI Mem Address = ffeffc00h 32bit length 1024 enabled
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = no connection
Device Dependent Registers:
0x40: 00 80 05 a3 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 04 00 00 00 00 00 00 00 00 00 00
0x60: 08 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00


Class = Serial Bus (SMBus)
Vendor ID = 8086h, Intel Corporation
Device ID = 24c3h, 82801DB SMBus Controller
PCI index = 0h
Class Codes = 0c0500h
Revision ID = 2h
Bus number = 0
Device number = 31
Function num = 3
Status Reg = 280h
Command Reg = 1h
I/O space access enabled
Memory space access disabled
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
PCI IO Address = 1880h length 32 enabled
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT B
Interrupt line = 5
CPU Interrupt = 5h
Device Dependent Registers:
0x40: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00


Class = Multimedia (Audio)
Vendor ID = 8086h, Intel Corporation
Device ID = 24c5h, 82801DB AC97 Audio Controller
PCI index = 0h
Class Codes = 040100h
Revision ID = 2h
Bus number = 0
Device number = 31
Function num = 5
Status Reg = 290h
Command Reg = 7h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
PCI IO Address = 1c00h length 256 enabled
PCI IO Address = 18c0h length 64 enabled
PCI Mem Address = e0100c00h 32bit length 512 enabled
PCI Mem Address = e0100800h 32bit length 256 enabled
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT B
Interrupt line = 5
CPU Interrupt = 5h
Capabilities Pointer = 50h
Capability ID = 1h
Capabilities = c9c2h - 0h
Device Dependent Registers:
0x40: 09 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 01 00 c2 c9 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 60 0f 00 00 00 00 00 00


Class = Network (Ethernet)
Vendor ID = 8086h, Intel Corporation
Device ID = 1078h, Unknown Unknown
PCI index = 0h
Class Codes = 020000h
Revision ID = 5h
Bus number = 1
Device number = 1
Function num = 0
Status Reg = 230h
Command Reg = 117h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 34h
Cache Line Size= 10h un-cacheable
PCI Mem Address = e0200000h 32bit length 131072 enabled
PCI IO Address = 2000h length 64 enabled
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 0ns
Min Gnt = 255ns
PCI Int Pin = INT A
Interrupt line = 5
CPU Interrupt = 5h
Capabilities Pointer = dch
Capability ID = 1h
Capabilities = 22h - 0h
Capability ID = 7h
Capabilities = 2h - 400000h
Device Dependent Registers:
0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 01 e4 22 00
0xE0: 00 00 00 00 07 00 02 00 00 00 40 00 00 00 00 00
0xF0: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00


Class = Bridge (PCI/PCI)
Vendor ID = 3388h, Hint Corp.
Device ID = 22h, Unknown Unknown
PCI index = 0h
Class Codes = 060400h
Revision ID = 4h
Bus number = 1
Device number = 4
Function num = 0
Status Reg = 2b0h
Command Reg = 107h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 1h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 21h
Cache Line Size= 10h un-cacheable
Primary Bus Number = 1h
Secondary Bus Number = 2h
Subordinate Bus Number = 2h
Secondary Latency Timer = fah
I/O Base = f1h
I/O Limit = 1h
Secondary Status = 2a0h
Memory Base = e030h
Memory Limit = e030h
Prefetchable Memory Base = fff1h
Prefetchable Memory Limit= 1h
Prefetchable Base Upper 32 Bits = 0h
Prefetchable Limit Upper 32 Bits = 0h
I/O Base Upper 16 Bits = ffffh
I/O Limit Upper 16 Bits = ffffh
Bridge Control = 4h
PCI Int Pin = NC
Interrupt line = 0
CPU Interrupt = 0h
Device Dependent Registers:
0x40: 00 00 04 00 00 00 00 02 00 00 10 00 10 10 10 10
0x50: 20 20 00 00 00 00 10 00 80 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 04 78 00 00 40 00 00
0x70: 01 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 01 e4 01 7e 00 00 00 00 06 e8 94 00 03 00 00 80
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00


Class = Network (Ethernet)
Vendor ID = 8086h, Intel Corporation
Device ID = 103ah, 82801DB LAN Controller with 82562ET/EZ (CNR)
PHY
PCI index = 0h
Class Codes = 020000h
Revision ID = 82h
Bus number = 1
Device number = 8
Function num = 0
Status Reg = 290h
Command Reg = 117h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 42h
Cache Line Size= 10h un-cacheable
PCI Mem Address = e0220000h 32bit length 4096 enabled
PCI IO Address = 2040h length 64 enabled
Subsystem Vendor ID = 1497h
Subsystem ID = c72h
Max Lat = 56ns
Min Gnt = 8ns
PCI Int Pin = INT A
Interrupt line = 5
CPU Interrupt = 5h
Capabilities Pointer = dch
Capability ID = 1h
Capabilities = fe22h - 3a004000h
Device Dependent Registers:
0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 22 fe
0xE0: 00 40 00 3a 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00


Class = Bridge (Unknown)
Vendor ID = 1895h, Unknown
Device ID = 1h, Unknown Unknown
PCI index = 0h
Class Codes = 068000h
Revision ID = 1h
Bus number = 2
Device number = 12
Function num = 0
Status Reg = 2b0h
Command Reg = 143h
I/O space access enabled
Memory space access enabled
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping enabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 8h un-cacheable
Max Lat = 26ns
Min Gnt = 8ns
PCI Int Pin = INT A
Interrupt line = 0
CPU Interrupt = 0h
Capabilities Pointer = 80h
Capability ID = 6h
Capabilities = 0h - 0h
Device Dependent Registers:
0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0xF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00


Class = Multimedia (Unknown)
Vendor ID = 1131h, Philips Semiconductors
Device ID = 7146h, SAA7146 Multi Media Bridge Scaler
PCI index = 0h
Class Codes = 048000h
Revision ID = 1h
Bus number = 2
Device number = 15
Function num = 0
Status Reg = 280h
Command Reg = 202h
I/O space access disabled
Memory space access enabled
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 7bh
Cache Line Size= 0h
PCI Mem Address = e0300000h 32bit length 512 enabled
Subsystem Vendor ID = 18c9h
Subsystem ID = 2011h
Max Lat = 38ns
Min Gnt = 15ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = bh
Device Dependent Registers:
0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x80: 00 00 00 80 00 00 00 80 00 00 00 80 00 00 00 80
0x90: 00 00 00 80 00 00 00 80 00 00 00 80 00 00 00 80
0xA0: 00 00 00 80 00 00 00 80 00 00 00 80 00 00 00 80
0xB0: 00 00 00 80 00 00 00 80 00 00 00 80 00 00 00 80
0xC0: 00 00 00 80 00 00 00 80 00 00 00 80 00 00 00 80
0xD0: 00 00 00 80 00 00 00 80 00 00 00 80 00 00 00 80
0xE0: 00 00 00 80 00 00 00 80 00 00 00 80 00 00 00 80
0xF0: 00 00 00 80 00 00 00 80 00 00 00 80 00 00 00 80

Daniel

Hi again,

I am not sure I understand. Looking at the report for the PCI/PCI
bridge (vendor ID: 3338h, device ID: 22h, device number 4, the IO and
memory space access are reported enabled. Does the fact that the
reported IO limit = 1h overwrite/cancel this report?

Does an address range (0xe03fffff - 0xe0300000) implies that the
maximum addressable memory on the new bridge (type “other”) is 1M
even if the card has more memory than this (64M)?

Class = Bridge (PCI/PCI)
Vendor ID = 3388h, Hint Corp.
Device ID = 22h, Unknown Unknown
PCI index = 0h
Class Codes = 060400h
Revision ID = 4h
Bus number = 1
Device number = 4
Function num = 0
Status Reg = 2b0h
Command Reg = 107h
I/O space access enabled
[b:f0e639a595]Memory space access enabled[/b:f0e639a595]
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 1h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 21h
Cache Line Size= 10h un-cacheable
Primary Bus Number = 1h
Secondary Bus Number = 2h
Subordinate Bus Number = 2h
Secondary Latency Timer = fah
I/O Base = f1h
[b:f0e639a595]I/O Limit = 1h[/b:f0e639a595]
Secondary Status = 2a0h
Memory Base = e030h
Memory Limit = e030h

I also read an article related to Linux that states :

‘the PCI bridges must be programmed with a base and limit for PCI I/O
and PCI Memory space access that they have to pass from their primary
bus onto their secondary bus. Once the PCI-PCI Bridges in a system
have been configured then so long as the Linux device drivers only
access PCI
I/O and PCI Memory space in these windows, the PCI-PCI Bridges are
invisible’

I am currently investigating this and what how this translate for a
QNX platform, i.e. configuration registers to program, to what
value…

Do you have any additional details/comments on this statement above?

Thanks again
Daniel

The fact that the I/O space is enabled on the PCI/PCI bridge means that it
will accept I/O cycles, but it will not pass them on to the lower bus, due
to the fact that the I/O Limit register is less than the I/O Base. If you
look at the PCI/PCI bridge (Vend 0x8086 - Dev 0x244e) you will see that the
I/O Base and I/O Limit are programmed to 0x20. This means that I/O addresses
0x2000 - 0x2fff will be passed on to buses 1 and 2. Also, the memory base
and limit registers are programmed to 0xe020 and 0xe030 respectively. This
will allow memory addresses 0xe0200000 - 0xe03fffff on to buses 1 and 2.
The bridge (Vend 0x3388 - Dev 0x22) must be programmed with these address
ranges or a subset of them, so the I/O Base and Limit registers will have to
be programmed with 0x20. The memory base and limit registers are already
programmed and will allow addresses 0xe0300000 - 0xe03fffff through on to
bus 2.
If you require larger memory and I/O apertures, you will have to modify both
bridges to configure a larger address range for buses 1 and 2.

See my comment below.

“dlabonte” <labonte_d@yahoo-dot-ca.no-spam.invalid> wrote in message
news:e0hkca$pum$1@inn.qnx.com

Hi again,

I am not sure I understand. Looking at the report for the PCI/PCI
bridge (vendor ID: 3338h, device ID: 22h, device number 4, the IO and
memory space access are reported enabled. Does the fact that the
reported IO limit = 1h overwrite/cancel this report?

Does an address range (0xe03fffff - 0xe0300000) implies that the
maximum addressable memory on the new bridge (type “other”) is 1M
even if the card has more memory than this (64M)?

Class = Bridge (PCI/PCI)
Vendor ID = 3388h, Hint Corp.
Device ID = 22h, Unknown Unknown
PCI index = 0h
Class Codes = 060400h
Revision ID = 4h
Bus number = 1
Device number = 4
Function num = 0
Status Reg = 2b0h
Command Reg = 107h
I/O space access enabled
[b:f0e639a595]Memory space access enabled[/b:f0e639a595]
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Header type = 1h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 21h
Cache Line Size= 10h un-cacheable
Primary Bus Number = 1h
Secondary Bus Number = 2h
Subordinate Bus Number = 2h
Secondary Latency Timer = fah
I/O Base = f1h
[b:f0e639a595]I/O Limit = 1h[/b:f0e639a595]
Secondary Status = 2a0h
Memory Base = e030h
Memory Limit = e030h

I also read an article related to Linux that states :

‘the PCI bridges must be programmed with a base and limit for PCI I/O
and PCI Memory space access that they have to pass from their primary
bus onto their secondary bus. Once the PCI-PCI Bridges in a system
have been configured then so long as the Linux device drivers only
access PCI
I/O and PCI Memory space in these windows, the PCI-PCI Bridges are
invisible’

I am currently investigating this and what how this translate for a
QNX platform, i.e. configuration registers to program, to what
value…

Do you have any additional details/comments on this statement above?

No, the statement above is correct.

Thanks again
Daniel