devb-eide on PowerPC

QNX Newsgroups (Archives) qnx.rtos
1

Hi all,

plans are to connect a CompactFlash Card onto custom hardware and to map the
ATA registers somewhere in the address space.

I remember the “stride” parameter for devb-eide that allows “holes” between
the distinct ATA registers - it is my understanding, that this is needed on
platforms where the registers can’t be accessed on their “normally
un-aligned” addresses.

stride=space Set the spacing offset between I/O ports (IDE command registers). E.g. if the ports are located on 4-byte boundaries, set space to 4. The default is 1.

Does devb-eide always access the registers in a Byte fashion, or do we have
to manipulate the addresses for the registers on the hardware (to prevent
alignment errors)?

And then: with flash access times so short: does devb-eide need an interrupt
for PIO modes or not? No plans to support DMA transfer so far.

regards
Peter

2

ping

Peter Wächtler wrote:

Hi all,

plans are to connect a CompactFlash Card onto custom hardware and to map
the ATA registers somewhere in the address space.

I remember the “stride” parameter for devb-eide that allows “holes”
between the distinct ATA registers - it is my understanding, that this is
needed on platforms where the registers can’t be accessed on their
“normally un-aligned” addresses.

cite utility docs
stride=space
Set the spacing offset between I/O ports (IDE command registers). E.g. if
the ports are located on 4-byte boundaries, set space to 4. The default is
1.
/cite

Does devb-eide always access the registers in a Byte fashion, or do we
have to manipulate the addresses for the registers on the hardware (to
prevent alignment errors)?

And then: with flash access times so short: does devb-eide need an
interrupt for PIO modes or not? No plans to support DMA transfer so far.

regards
Peter

3

Peter W??chtler <qnxcon@mac.com> wrote:

Hi all,

plans are to connect a CompactFlash Card onto custom hardware and to map the
ATA registers somewhere in the address space.

I remember the “stride” parameter for devb-eide that allows “holes” between
the distinct ATA registers - it is my understanding, that this is needed on
platforms where the registers can’t be accessed on their “normally
un-aligned” addresses.

cite utility docs
stride=space
Set the spacing offset between I/O ports (IDE command registers). E.g. if
the ports are located on 4-byte boundaries, set space to 4. The default is
1.
/cite

Does devb-eide always access the registers in a Byte fashion, or do we have
to manipulate the addresses for the registers on the hardware (to prevent
alignment errors)?

It uses 16 bit access for the data register and 8 bit for the others.

And then: with flash access times so short: does devb-eide need an interrupt
for PIO modes or not?

The driver requires an interrupt.

4

Kevin Chiles wrote:

Does devb-eide always access the registers in a Byte fashion, or do we
have to manipulate the addresses for the registers on the hardware (to
prevent alignment errors)?

It uses 16 bit access for the data register and 8 bit for the others.

OK, then I’m expecting the driver to “just work” with the given register
set. Thanx.

Peter

from ATA-2 FAQ:
3.1.4 How are the Task File and data I/O ports assigned?
!
! The Task File registers and the data register of the primary ATA
! channel occupy the following I/O addresses (in hexadecimal notation):
!
! Register Read Function Write Function
!
! 1F0 Read Data Write Data
! (16 Bits) (16 bits)
! 1F1 N/A Set Features Data
! 1F2 Status of sector Write sector count
! count for command setup
! 1F3 Location of starting Write sector start
! sector for command setup
! 1F4 Location of Cyl-low Write cyl-low location
! for command setup
! 1F5 Location of Cyl-high Write cyl-high location
! for command setup
! 1F6 Head/device selection Write device selection
! and head selection for
! command setup
! 1F7 Device Status Device command