I am trying to write a ISR to service an external interrupt on the SH4 processor. The interrupt is generated by an FPGA when a CAN controller recieves a CAN message (the CAN controller is also connected to the FPGA). I want the ISR (or actually a thread that is activated by the ISR, on arrival of an interrupt) to read the CAN message data from the FPGA. The FPGA will clear the interrupt once all the message bytes have been read.
To this end, I have modified the SolutionEngine BSP code to set up the SH4 external interrupts as 4 independant interrupt request lines, in stead of priority encoded interrupts. I have also implemented an interrupt handler by means of InterruptAttachEvent(). The event is simply a SIGEV_INTR event that signals the interrupt servicing thread to start reading CAN data.
The code for setting up the interrupts in the image is: (taken from init_intrinfo.c)
const static struct startup_intrinfo intrs[] = {
…other interrupts…
{ SH_INTR_CLASS_EXTERNAL, 4, _NTO_INTR_SPARE,
SH_EXC_INTR, 0, 0,
{0, 0, &interrupt_id_ext},
{INTR_GENFLAG_LOAD_INTRMASK, 0, interrupt_eoi_ext},
&interrupt_mask_ext, &interrupt_unmask_ext, 0,
},
and to set the external interrupts as 4 independant ir lines:
/* init ICR - program IRL’s for separate interrupts */
//ICR bit 7 = IRLM (IRL pin Mode) :
//set to 0 : IRL pins used as level-encoded interrupt requests
//set to 1 : IRL pins used as 4 independant interrupt requests
out16(SH_MMR_INTC_ICR, 0x128);
My problem is - the QNX kernel crashes as soon as the interrupt occurs. It would appear that the crash occurs even before my handler gets a chance to execute, and i’m fairly sure the problem isn’t the interrupt handler itself - I can successfully attach an interrupt handler to the timer.
My guess would be that the interrupt isn’t masked properly, but I don’t know how to test for this condition (any attempt to set a breakpoint inside the ISR results in a kernel crash anyway).
Does anyone have advice?