memory mapped i/o on qnx neutrino (newbie)

QNX Newsgroups (Archives) comp.os.qnx
1

I would like to use the parallel port in QNX to drive master-mode SPI
devices. I got it to work, but it’s too slow. It seems to boil down to the
time it takes to do the assembly in and out instructions, which (on a PIII
600 I tried it on), was about 50 times slower than just writing to memory.
I checked in Windows, and the order-of-magnitude difference was there also.

From reading intel architecture docs, I understand it’s possible to use
memory-mapped I/O instead of the in and out instructions, provided that
caching is disabled for the mapped pages. Because the in and out
instructions wait for an acknowledgement before executing the next
instruction (and the memory mapped IO does not), I am hoping this route will
solve my current problem.

However, I don’t know how to do this in neutrino (or any other OS for that
matter). I tried using mmap_device_io(), but the call was not consistent
with the documentation (which hinted they wouldn’t do anything useful on
intel hardware anyway).

Can someone shove me in the right direction? Thanks in advance,

Warren MacEvoy

2

You can’t do this. It won’t work. Your problem is that you
are dealing with a very ancient piece of hardware, the parallel
port. It will only go as fast as it will go. The problem
is not the inp() or outp() isntructions. Sorry.

Previously, Warren MacEvoy wrote in comp.os.qnx:

I would like to use the parallel port in QNX to drive master-mode SPI
devices. I got it to work, but it’s too slow. It seems to boil down to the
time it takes to do the assembly in and out instructions, which (on a PIII
600 I tried it on), was about 50 times slower than just writing to memory.
I checked in Windows, and the order-of-magnitude difference was there also.

From reading intel architecture docs, I understand it’s possible to use
memory-mapped I/O instead of the in and out instructions, provided that
caching is disabled for the mapped pages. Because the in and out
instructions wait for an acknowledgement before executing the next
instruction (and the memory mapped IO does not), I am hoping this route will
solve my current problem.

However, I don’t know how to do this in neutrino (or any other OS for that
matter). I tried using mmap_device_io(), but the call was not consistent
with the documentation (which hinted they wouldn’t do anything useful on
intel hardware anyway).

Can someone shove me in the right direction? Thanks in advance,

Warren MacEvoy


\

–
Mitchell Schoenbrun --------- maschoen@pobox.com

3

Hi Warren

“Warren MacEvoy” <wmacevoy@mesastate.edu> wrote:

I would like to use the parallel port in QNX to drive master-mode SPI
devices. I got it to work, but it’s too slow. It seems to boil down to the
time it takes to do the assembly in and out instructions,
Very True



which (on a PIII
600 I tried it on), was about 50 times slower than just writing to > memory.
It SHOULD be even more… u may be using a faster RAM than mine

Even a PIV 1GHz wont help… PC-AT hardware spec are like that (remember the
“jmp $+2” sequences… littered up in the communications and hardware driver
software used to insert small delays) actually the PC-AT PCI timing is a bit
off, it requires timing synchonization to work properly which is done by the
(qnx)library… (things are a “bit” better in linux device drivers where you
have both functions… with-in-built-delay and non-inbuilt-ones)

If by any chance you are using ECP parallel port (i’m sure u have one, as no
PIII motherboard comes without a EPP+ECP parallel port, though u may have to
enable the ECP mode and select the DMA channel through BIOS), use DMA to
transfer data… it will be HELL FASTER than manually doing it. BTW i dont
have a hands on experience with ECP/EPP parallel ports, if you have follow it
on to me too, please :wink:

I checked in Windows, and the order-of-magnitude difference was >there also.
same difference…



From reading intel architecture docs, I understand it’s possible to use
memory-mapped I/O instead of the in and out instructions, provided that
caching is disabled for the mapped pages.

Nope… no way now, I think its done only on a sun sparc, (it is the ONLY way
on that hardware)

Because the in and out
instructions wait for an acknowledgement before executing the next
instruction

No… they wait for the timing signal… (as per best of my belief… correct
me if i’m wrong)

(and the memory mapped IO does not),
If it wont (if at all, in theory), it will mess up your data



I am hoping this route will
solve my current problem.

I think the ECP way can… also try EPP though i dont know how much better is
it than SPP

However, I don’t know how to do this in neutrino (or any other OS for that
matter). I tried using mmap_device_io(), but the call was not consistent
with the documentation (which hinted they wouldn’t do anything useful on
intel hardware anyway).

on intel directly do out8(0x378, mydata), no mmap_device_io is explicitely
required… it is there only for cross platform consistency

Hope that’s helpful, do let me know of developments

–
Keep Smiling

Mechanically Yours

  • Mritunjai

A ship ought not to be held by one anchor, nor life by a single hope.

Sophomore Undergraduate
Mechanical Engg.
Indian Institute of Technology Bombay
India


Sent via Deja.com
http://www.deja.com/

4

Akhilesh Mritunjai <akhileshmritunjai@rediffmail.com> wrote in message
news:927acu$f34$1@nnrp1.deja.com…

From reading intel architecture docs, I understand it’s possible to use
memory-mapped I/O instead of the in and out instructions, provided that
caching is disabled for the mapped pages.

Nope… no way now, I think its done only on a sun sparc, (it is the ONLY
way
on that hardware)

Let me try to clarify…

The Intel CPU architecture will allow memory-mapped I/O.
HOWEVER, the actual hardware device must be built by the manufacturer to use
memory-mapped I/O in order for it to work.
Almost all (I think I know of at least one exception) printer port hardware
will absolutely NOT use memory mapped I/O to the printer port!