“Mario Charest” <mcharest@void_zinformatic.com> wrote in message
news:916k18$j86$1@nntp.qnx.com…
“Warren Peece” <> warren@nospam.com> > wrote in message
news:9169l4$d1n$> 1@inn.qnx.com> …
For the data portion you coulc leave cache on since only the CPU modifies
the data (assuming your flash is not paged)
However for control address “write/erase complete” the data must not
be cacheable for obvious reason.
Yup, it would be a bad thing™
However I’m not sure using the cache of the CPU for flash data is
a good idea. Data in FLASH is scatter all over the place,
very bad for cache trashing. However given that the cache is MUCH
faster then flash it could be worth investigating. I beleive the cache
is usually filled doing burst read ahead, again given the spaghetti
type of data arrengement those extra read could impose a penality (I’m
just guessing how the Pentium works here, maybe it’s smarter then I think
it is)
This is for my embedded thingie which is 486 based, so it aint that smart
about caching (and doesn’t have very much of it, to boot). It’s not going
to be a huge hit if I don’t cache stuff, I may not notice a difference at
all except if I happen to go with small, frequently read files which in that
case I’d just suck 'em into RAM. It’s more of an academic question, really,
and I also have another P133 embedded design on the drawing board that may
or may not be able to take advantage of more betterer cachingism.
How about mmap the memory twice, one with NOCACHE and the
other one without?
If I’m reading from the cached pointer, then I hit the nocache pointer and
erase the device, the cached pointer isn’t going to reflect the change (to
all 0xFF). I would think I’d need something like turn off caching, do my
writes/erases, turn on caching and invalidate all cache lines in a certain
address range.
My guess is it aint gonna happen, but I thought I’d see if anyone had any
cute tricks I could play with.
-Warren “can never have too much cash” Peece