Interrupt hardware priority reassignment

QNX Newsgroups (Archives) qdn.public.qnxrtp.os
1

Hi Folks,

I have written an interrupt handler in QNX 6.1, and through profiling have
discovered that the ISR-to-thread latency is ~4.7usec 99.8% of the time but
on occassion this latency jumps to 12usec – a 2.5x increase – and, more
often, various points in between.

Now, I have my suspicions I’m being pre-empted by higher-priority interrupts
considering my thread is FIFO-scheduled and has a higher priority than
anything else – what else would/could pre-empt it?

In QNX’s “Neutrino Microkernel” docs, in the “Interrupt Handling” section, it
states:

“Since hardware interrupt priorities can be reassigned, the most
important interrupt in the system can be made the highest priority.”

How do I do this??? How do I even determine what priority my interrupt is
in relation to others???

– Pete

2

“Peter Sommerfeld” <peter@qnx.com> wrote in message
news:9u31s9$e7h$1@inn.qnx.com…

Hi Folks,

I have written an interrupt handler in QNX 6.1, and through profiling have
discovered that the ISR-to-thread latency is ~4.7usec 99.8% of the time
but
on occassion this latency jumps to 12usec – a 2.5x increase – and, more
often, various points in between.

Now, I have my suspicions I’m being pre-empted by higher-priority
interrupts
considering my thread is FIFO-scheduled and has a higher priority than
anything else – what else would/could pre-empt it?

Bad hardware and SMI mode.

In QNX’s “Neutrino Microkernel” docs, in the “Interrupt Handling” section,
it
states:

“Since hardware interrupt priorities can be reassigned, the most
important interrupt in the system can be made the highest priority.”

They can only be reassign if you create a custom board support
package.

How do I do this??? How do I even determine what priority my interrupt is
in relation to others???

It’s fixed,flow high to low: 3,4,5,6,7,0,1,2,8,9,10,11,12,13,14,15


\

– Pete

3

Well I don’t think SMI is killing - as far as I know it’s an x86 thing and I’m
on a PowerPC. I think I can rule out hardware after profiling the read
and write to hardware involved in checking/clearing the interrupt source. A
histogram of 400,000 reads and writes shows very little deviation.


Mario Charest <mcharest@clipzinformatic.com> wrote:

“Peter Sommerfeld” <> peter@qnx.com> > wrote in message
news:9u31s9$e7h$> 1@inn.qnx.com> …
Hi Folks,

I have written an interrupt handler in QNX 6.1, and through profiling have
discovered that the ISR-to-thread latency is ~4.7usec 99.8% of the time
but
on occassion this latency jumps to 12usec – a 2.5x increase – and, more
often, various points in between.

Now, I have my suspicions I’m being pre-empted by higher-priority
interrupts
considering my thread is FIFO-scheduled and has a higher priority than
anything else – what else would/could pre-empt it?

Bad hardware and SMI mode.


In QNX’s “Neutrino Microkernel” docs, in the “Interrupt Handling” section,
it
states:

“Since hardware interrupt priorities can be reassigned, the most
important interrupt in the system can be made the highest priority.”


They can only be reassign if you create a custom board support
package.

How do I do this??? How do I even determine what priority my interrupt is
in relation to others???


It’s fixed,flow high to low: 3,4,5,6,7,0,1,2,8,9,10,11,12,13,14,15

– Pete

4

Peter Sommerfeld <peter@qnx.com> wrote:

Hi Folks,

I have written an interrupt handler in QNX 6.1, and through profiling have
discovered that the ISR-to-thread latency is ~4.7usec 99.8% of the time but
on occassion this latency jumps to 12usec – a 2.5x increase – and, more
often, various points in between.

Now, I have my suspicions I’m being pre-empted by higher-priority interrupts
considering my thread is FIFO-scheduled and has a higher priority than
anything else – what else would/could pre-empt it?

In QNX’s “Neutrino Microkernel” docs, in the “Interrupt Handling” section, it
states:

“Since hardware interrupt priorities can be reassigned, the most
important interrupt in the system can be made the highest priority.”

How do I do this??? How do I even determine what priority my interrupt is
in relation to others???

– Pete

I should note my e-mail is not “peter@qnx.com” – otherwise I probably
wouldn’t be asking for help!!! I don’t know where it’s pulling that address
from … oh well

5

Peter Sommerfeld wrote:

Well I don’t think SMI is killing - as far as I know it’s an x86 thing and I’m
on a PowerPC. I think I can rule out hardware after profiling the read
and write to hardware involved in checking/clearing the interrupt source. A
histogram of 400,000 reads and writes shows very little deviation.

Well, if you’re on PowerPC (and presumably using a bsp), then it should’nt be

onerous to set the hardware interrupt priority in the startup code (as Mario

suggested).

I think that the section of documentation you posted implies that QNX
itself is unaffected by changing of the interrupt priority (which I
believe to be true), but AFAIK there is no abstracted API for
programming an interrupt controller (probably because this is something
that is almost certainly done only once when the hardware is being set up).

btw: a worst case of 12usec doesn’t sound that bad for a PPC (they
potentially have a lot of registers to save don’t they ?) depending on
processor speed, and if, in fact, your handler is being pre-empted by
another interrupt.

6

As far as i know it’s not fixed for (PIC programable interrupt
controller) (or APIC).

I meant fixed as in can’t be change through OS config or API.
QNX4 does have an option to change interrupt priority

But it’s cycled - you pick the first and all
others are next. I’m not sure the numbers (i thought they’re different
but i won’t insist), but in this case it can be
5,6,7,0,1,2,8,9,10,11,12,13,14,15,3,4. It’s not hard to reprogram it,
but would NTO like it? =) I neved did this.

All document I read from QNX strongly discourage interfering
with the PIC. I think it would be asking for trouble to do so :wink:

7

Mario Charest wrote:

“Peter Sommerfeld” <> peter@qnx.com> > wrote in message
news:9u31s9$e7h$> 1@inn.qnx.com> …
Hi Folks,

I have written an interrupt handler in QNX 6.1, and through profiling have
discovered that the ISR-to-thread latency is ~4.7usec 99.8% of the time
but
on occassion this latency jumps to 12usec – a 2.5x increase – and, more
often, various points in between.

Now, I have my suspicions I’m being pre-empted by higher-priority
interrupts
considering my thread is FIFO-scheduled and has a higher priority than
anything else – what else would/could pre-empt it?

Bad hardware and SMI mode.


In QNX’s “Neutrino Microkernel” docs, in the “Interrupt Handling” section,
it
states:

“Since hardware interrupt priorities can be reassigned, the most
important interrupt in the system can be made the highest priority.”


They can only be reassign if you create a custom board support
package.

How do I do this??? How do I even determine what priority my interrupt is
in relation to others???


It’s fixed,flow high to low: 3,4,5,6,7,0,1,2,8,9,10,11,12,13,14,15
As far as i know it’s not fixed for (PIC programable interrupt

controller) (or APIC). But it’s cycled - you pick the first and all
others are next. I’m not sure the numbers (i thought they’re different
but i won’t insist), but in this case it can be
5,6,7,0,1,2,8,9,10,11,12,13,14,15,3,4. It’s not hard to reprogram it,
but would NTO like it? =) I neved did this.

8

It does sound a lot like another interrupt handler is getting in the way.
However, I don’t think that changing interrupt priorities will help you very
much, since the time you’re concerned about is the time from the completion
of the ISR to the start of execution of your thread. Even if your interrupt
has the highest priority, a lower priority interrupt will still take
precedence over your thread.

If you really need to do something very quickly in response to an interrupt,
then you’ll probably have to do the work in the ISR.

Regards,

Bert Menkveld
Engineer
Corman Technologies Inc.

“Peter Sommerfeld” <peter@qnx.com> wrote in message
news:9u31s9$e7h$1@inn.qnx.com…

Hi Folks,

I have written an interrupt handler in QNX 6.1, and through profiling have
discovered that the ISR-to-thread latency is ~4.7usec 99.8% of the time
but
on occassion this latency jumps to 12usec – a 2.5x increase – and, more
often, various points in between.

Now, I have my suspicions I’m being pre-empted by higher-priority
interrupts
considering my thread is FIFO-scheduled and has a higher priority than
anything else – what else would/could pre-empt it?

In QNX’s “Neutrino Microkernel” docs, in the “Interrupt Handling” section,
it
states:

“Since hardware interrupt priorities can be reassigned, the most
important interrupt in the system can be made the highest priority.”

How do I do this??? How do I even determine what priority my interrupt is
in relation to others???

– Pete