David Gibbs <email@example.com> wrote in article <firstname.lastname@example.org>…
ISA and PCI are different buses – the BIG difference for irqs is that
ISA uses edge-triggered interrupts,
There is no limitation in PC/AT (pure ISA). You are able to program interrupt controller to work as
you’d like (see port 0x20, bit 3 of the first control word).
but PCI uses level-triggered interrupts.
You can share interrupts (assuming the drivers are bright enough) in a
level-triggered environment but not edge-triggered.
Why? There is small probability to miss the interrupt, but only if you have ISA card’s hardware
which wasn’t designed for such purposes (the all ISA cards, as a rule) or if you do mistake in ISR.
For exampe, I worked with our own ISA card, it has status register (port) to see interrupt request
bit on card and control register (port) to rise up interrupt line back - I guess it has enough
hardware to share interrupt even in edge-trigged environment. You just have to do polling of
another card as last step in your ISR. Theoreticly it is possible and, of course, level-trigged
interrupts are preferable in this case. I think the main reason it was not used in old ISA days is
because there is only one quite solid answer: if your device require to send interrupt request,
take a free interrupt line for your device. IMO it is not always good to have ISR’s train instead
of an ISR, it is not knowen in which carriage is my ISR… So, PCI interrupt sharing is some kind
of multi-media… You have many things, but they are not quite well… It’s only my opinion
This rules out the above requested configuration.
(So, how does Windows handle com1 & com3 having the same IRQ? Polling.)
I’m not impressed by this windows behaviour.
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