My question is, does QNX set up the PICs to use edge- or level triggered IRQ
handling ?
According to an earlier thread, edge mode is preferred for ISA peripherals,
whereas level triggering is used by PCI (to allow interrupt sharing). To my
understanding, the PIC can use only one mode for all IRQs. So, which one
does QNX use ? Can it be configured ? Is there an API to set this up ? Would
the system reliably tolerate direct manipulation of this setting in the PIC
?
As I have found no clear statement on these questions, could one of you shed
some light on this ?
My question is, does QNX set up the PICs to use edge- or level triggered IRQ
handling ?
According to an earlier thread, edge mode is preferred for ISA peripherals,
whereas level triggering is used by PCI (to allow interrupt sharing). To my
understanding, the PIC can use only one mode for all IRQs. So, which one
does QNX use ? Can it be configured ? Is there an API to set this up ? Would
the system reliably tolerate direct manipulation of this setting in the PIC
?
ISA (and other electrically similar buses) are edge-triggered, in particular
they’re rising edge triggered. PCI (and other electrically similar buses,
e.g. CompactPCI) are level-triggered.
Yes, both behaviours can co-exist on x86 pc systems. Not sure exactly
how this is handled at the hardware level, ie for configuration of the
8259(s), or whether the PCI bus hardware fakes something out at its
level before delivering a signal to the 8259.
As to tolerating direct manipulation of the PIC – QNX would not
tolerate this behaviour.
Friedrich Ensslin <> friedrich.ensslin@am3.com> > wrote:
We are using RTP 6.1A on a PC-style Hardware.
My question is, does QNX set up the PICs to use edge- or level triggered IRQ
handling ?
According to an earlier thread, edge mode is preferred for ISA peripherals,
whereas level triggering is used by PCI (to allow interrupt sharing). To my
understanding, the PIC can use only one mode for all IRQs. So, which one
does QNX use ? Can it be configured ? Is there an API to set this up ? Would
the system reliably tolerate direct manipulation of this setting in the PIC
?
ISA (and other electrically similar buses) are edge-triggered, in particular
they’re rising edge triggered. PCI (and other electrically similar buses,
e.g. CompactPCI) are level-triggered.
Yes, both behaviours can co-exist on x86 pc systems. Not sure exactly
how this is handled at the hardware level,
Yes, every 8259A can be programmed to be level or edge sensitive. But look for Intel’s 82371AB PCI
ISA IDE Xcelerator (PIIX4) reference (just an example for nowadays):
ELCR1-Edge/Level Control Register (IO)
I/O Addr: INT CNTRL-1-4D0h: select trigged mode for IRQ[3:7], IRQ[0:2] are always edge sensitive.
ELCR2-Edge/Level Control Register (IO)
I/O Addr: INT CNTRL-2-4D1h: select trigged mode for IRQ[15,14,12:9], IRQ[13,8] are always edge
sensitive.
So, it depends on what you mean by “PC-style Hardware”
Does that mean, that the IRQs coming from an ISA source are always
configured as edge-triggered, and those coming from a PCI source must use
level triggering, and there’s no way to change this on a QNX RTP ?
Anybody else around here, who might know about how these two strategies are
combined, although the PICs themselves cannot combine different modes ? Is
it a feature of PCI chipsets ?
Friedrich Ensslin <> friedrich.ensslin@am3.com> > wrote:
We are using RTP 6.1A on a PC-style Hardware.
My question is, does QNX set up the PICs to use edge- or level triggered
IRQ
handling ?
According to an earlier thread, edge mode is preferred for ISA
peripherals,
whereas level triggering is used by PCI (to allow interrupt sharing). To
my
understanding, the PIC can use only one mode for all IRQs. So, which one
does QNX use ? Can it be configured ? Is there an API to set this up ?
Would
the system reliably tolerate direct manipulation of this setting in the
PIC
?
ISA (and other electrically similar buses) are edge-triggered, in
particular
they’re rising edge triggered. PCI (and other electrically similar buses,
e.g. CompactPCI) are level-triggered.
Yes, both behaviours can co-exist on x86 pc systems. Not sure exactly
how this is handled at the hardware level, ie for configuration of the
8259(s), or whether the PCI bus hardware fakes something out at its
level before delivering a signal to the 8259.
As to tolerating direct manipulation of the PIC – QNX would not
tolerate this behaviour.
Does that mean, that the IRQs coming from an ISA source are always
configured as edge-triggered, and those coming from a PCI source must use
level triggering, and there’s no way to change this on a QNX RTP ?
Are you going to use non-standard PCI card? That way is not bad for all devices in PCI
specification suit. I think you can change this on your own risk
Anybody else around here, who might know about how these two strategies are
combined, although the PICs themselves cannot combine different modes ? Is
it a feature of PCI chipsets ?
Does that mean, that the IRQs coming from an ISA source are always
configured as edge-triggered, and those coming from a PCI source must use
level triggering, and there’s no way to change this on a QNX RTP ?
That is how we configure things. That is, also, the expected behaviour
for the buses involved. e.g. if you have a PCI bios configuring your
cards on the PCI bus, it will allow multiple cards to share the same
interrupt line – it is only safe to do this in a level-triggered interrupt
environment.
As to “no way to change this”, well, you can modify the IPL, you can
modify the startup, you can configure the PIC, and you can replace the
code that the kernel uses to deal with the PIC.
But, I don’t know how “hard-coded” the level vs edge is at the bus-controller
levels.