In some threads concerning real-time performance (e.g. most recently “ISR misses interrupts”)
the System Management Mode of x86 has come up. I was wondering if help could
be placed in Neutrino for dealing with this. If it cant be disabled, could we at
least find out if it’s being entered? From what I read it is entered via SMI as
an interrupt. Where is this interrupt code? In the BIOS? For someone who is
locked into using PC’s for real-time, SMM is scary.
–
Art Hays
National Institutes of Health
avhays@nih.gov
Art Hays <avhays@nih.gov> wrote:
In some threads concerning real-time performance (e.g. most recently “ISR misses interrupts”)
the System Management Mode of x86 has come up. I was wondering if help could
be placed in Neutrino for dealing with this. If it cant be disabled, could we at
least find out if it’s being entered? From what I read it is entered via SMI as
an interrupt. Where is this interrupt code? In the BIOS? For someone who is
locked into using PC’s for real-time, SMM is scary.
My understanding of System Management Mode, is that it is supposed to be
“completely transparent to the operating system”, that is, the operating
system never knows that it went into, or came out of, SMM.
I think it is handled by BIOS code.
Yes, SMM is scary.
-David
QNX Training Services
http://www.qnx.com/support/training/
Please followup in this newsgroup if you have further questions.
Is SMM implemented in AMD’s processors? So far I have only seen it in Intels
lineup.
E.
David Gibbs <dagibbs@qnx.com> wrote:
Art Hays <> avhays@nih.gov> > wrote:
In some threads concerning real-time performance (e.g. most recently “ISR misses interrupts”)
the System Management Mode of x86 has come up. I was wondering if help could
be placed in Neutrino for dealing with this. If it cant be disabled, could we at
least find out if it’s being entered? From what I read it is entered via SMI as
an interrupt. Where is this interrupt code? In the BIOS? For someone who is
locked into using PC’s for real-time, SMM is scary.
My understanding of System Management Mode, is that it is supposed to be
“completely transparent to the operating system”, that is, the operating
system never knows that it went into, or came out of, SMM.
I think it is handled by BIOS code.
Yes, SMM is scary.
-David
QNX Training Services
http://www.qnx.com/support/training/
Please followup in this newsgroup if you have further questions.
Back about March 1997, Dr Dobb’s Journal had some articles about SMM on
the original Pentium in their “Undocumented Corner”. It might still be
in their online archives, or on the CD certainly. I had tried to print
it out, but Netscrape chopped off one side, so it wasn’t too useful.
Afraid I don’t remember the details, anyway, just enough to not want to
deal with it.
Phil Olynyk
OBT Software Corp.
David Gibbs wrote:
Art Hays <> avhays@nih.gov> > wrote:
In some threads concerning real-time performance (e.g. most recently “ISR misses interrupts”)
the System Management Mode of x86 has come up. I was wondering if help could
be placed in Neutrino for dealing with this. If it cant be disabled, could we at
least find out if it’s being entered? From what I read it is entered via SMI as
an interrupt. Where is this interrupt code? In the BIOS? For someone who is
locked into using PC’s for real-time, SMM is scary.
My understanding of System Management Mode, is that it is supposed to be
“completely transparent to the operating system”, that is, the operating
system never knows that it went into, or came out of, SMM.
I think it is handled by BIOS code.
Yes, SMM is scary.
-David
QNX Training Services
http://www.qnx.com/support/training/
Please followup in this newsgroup if you have further questions.
Art Hays <avhays@nih.gov> wrote:
In some threads concerning real-time performance (e.g. most recently “ISR misses interrupts”)
the System Management Mode of x86 has come up. I was wondering if help could
be placed in Neutrino for dealing with this. If it cant be disabled, could we at
least find out if it’s being entered? From what I read it is entered via SMI as
an interrupt. Where is this interrupt code? In the BIOS? For someone who is
locked into using PC’s for real-time, SMM is scary.
The Intel Architechture Software Developers Manual (Vol. 3) has a chapter
on it.
The gist of it is that SMI in non-maskable, and takes precedence over all
other interrupts including NMI. A special area of RAM, called SMRAM,
is used to store the SMI interrupt handler code, data, and stack, and
to save processor context upon entry to system management mode.
Since an external pin (SMIACT) is asserted when the system enters SMM mode,
this RAM can be hidden from the OS (the SMIACT pin can be used as
part of the address decode). The default location for SMRAM is
0x30000, and can only be relocated by the SMI handler.
So typically, the SMI interrupt is handled by the BIOS, and the OS cannot
hook the SMI interrupt. SMI is triggered by circuitry external to the
CPU. Typical applications are power management, or software emulation
of hardware (e.g. with USB keyboards, a PS/2 style keyboard may be
emulated by having accesses to port 0x60 assert SMI, then the SMI
handler can decode the attempted I/O instruction, and talk to the
USB hardware under the covers).
Yes, they did a great job of making it transparent to the OS 
You really need to talk to your system supplier for details on what
could trigger assertion of the SMI pin. Usually, there are various
BIOS settings that can be selected that will reduce or eliminate
SMI assertion. If your system supplier is not interested in
helping, you could sever the SMI pin going to the CPU
(it’s been done before 
Dave
Hardware Support Account <hw@qnx.com> wrote:
Is SMM implemented in AMD’s processors? So far I have only seen it in Intels
lineup.
Don’t know about AMD, but the NatSemi Geode processors have something
equivalent, whereby I/O ports for certain devices are emulated in
software.
Dave