Miguel Simon wrote:
I registered with motorola, put a service request to the MPC555 site,
and they answered back with the web page:
“In reply to your Service Request SR 1-14042917 (see details below):
Yes the MPC555 has the MMU in the chip, we have a data book up on the
web
http://www.mcu.motsps.com/documentation/index.html> . I hope this helps.”
I have not seen the web page since their server is down (I subsequently
asked about their down web, and they acknowledge that it is down
momentarily):
" Yes the link is down please try again later if not please go into the
main site > http://www.mot.com/SPS/ > again sorry about that."
Weird. The link works fine for me, but reference to Data Book is bogus.
There is Reference Manual document, it is 14Mb PDF file and it does not
have a single occurence of word ‘MMU’. Data sheets available at URLs
below also do not mention MMU.
I have not been there yet, but I guess that I’ll take their word for now
(I’ll try later at another time).
Igor Kovalenko wrote:
Hmmm. How do you know it has MMU? Out of curiosity I went through all
pages related to MPC555 and did not find any reference to MMU. It looks
like MMU is part of OEA level of PowerPC architecture and MPC5xx series
does not adhere to it.
Please enlighten me if you would, ‘OEA level’ means…?
It is described in PowerPC Microprocessors Family Programming
Environment docment. There are 3 levels of architecture: UISA, VEA
(includes UISA) and OEA (includes VEA). Implementations are free to
choose whatever level they deem sufficient. MMU is defined at OEA level,
which is probably why some PPC processors have MMU but some do not.
Here is quote from document if you can’t access it:
The three levels of the PowerPC architecture are defined as follows:
• PowerPC user instruction set architecture (UISA)—The UISA defines the
level of
the architecture to which user-level (referred to as problem state in
the architecture
specification) software should conform. The UISA defines the base
user-level
instruction set, user-level registers, data types, floating-point memory
conventions
and exception model as seen by user programs, and the memory and
programming
models. The icon shown in the margin identifies text that is relevant
with respect to
the UISA.
• PowerPC virtual environment architecture (VEA)—The VEA defines
additional
user-level functionality that falls outside typical user-level software
requirements.
The VEA describes the memory model for an environment in which multiple
devices can access memory, defines aspects of the cache model, defines
cache
control instructions, and defines the time base facility from a
user-level perspective.
The icon shown in the margin identifies text that is relevant with
respect to the VEA.
Implementations that conform to the PowerPC VEA also adhere to the UISA,
but
may not necessarily adhere to the OEA.
• PowerPC operating environment architecture (OEA)—The OEA defines
supervisor-level
(referred to as privileged state in the architecture specification)
resources
typically required by an operating system. The OEA defines the PowerPC
memory
management model, supervisor-level registers, synchronization
requirements, and
the exception model. The OEA also defines the time base feature from a
supervisor-level
perspective. The icon shown in the margin identifies text that is
relevant with
respect to the OEA.
Implementations that conform to the PowerPC OEA also conform to the
PowerPC
UISA and VEA.
Ok, I am confused here. I guess that we have to wait to see if the
MPC555 does have MMUs or not.
Yeah, find a microscope and try to see it 
Good luck,
.