A devn-3gio driver maybe? Allow IPC accross the back plane?
They may have it in mind for massivly scalable SMP type stuff and need to
get their 2cents in for making sure it will support all sorts of cool stuff
they may have in mind?
Kevin
“Armin Steinhoff” <a-steinhoff@web_.de> wrote in message
news:3C7E9172.FCA00E64@web_.de…
Igor Kovalenko wrote:
I am not 3GIO expert so this is just my guess. The idea to use PCI
backplane as communication media for multi-node system is quite old and
there were implementations for QNX. It however was not really practical
because using PCI is such manner tends to be very CPU-intensive. It also
does not seem like a good idea in age of gigabit ethernet, assuming
current PCI bandwidth.
So perhaps QNX will try to make sure they can use 3GIO for efficient
inter-node communications.
Such a communication takes place at motherboard or backplane level
between a
3GIO bridge or switch and e.g. a 3GIO capable controller … that means
the communication happens at a very low hardware level.
How can it be optimized with QNX ??
Armin
Or perhaps they have something else in mind, what we don’t even think
about atm > 
Armin Steinhoff wrote:
Jens H Jorgensen wrote:
My understanding of 3GIO is that it is a replacement for PCI/AGP and
that it
will come in various configurations from x1 to x16 delivering from
200MBytes/s to 3.2GBytes/s (PCI is 133MBytes/s if I remember right).
There
is an article at extremetech.com which is worth reading:
http://www.extremetech.com/article/0,3396,s=201&a=23383,00.asp
More correct infos are at:
http://developer.intel.com/technology/3gio/
Any idea what QNX can do at this level??
How could QNX extend the performance of the 3GIO architecture ??
I have no clue …
Armin
–
Jens
“Armin Steinhoff” <a-steinhoff@web_.de> wrote in message
news:3C7E5820.BBB09D7B@web_.de…
Linda Campbell wrote:
“QNX is proud to deliver a highly reliable and scalable software
foundation that can extend the
performance of the 3GIO architecture. The development of this
interconnect is vital for the health of tomorrow’s networks, which
will
have to handle overwhelming bandwidth demands due to the
convergence of
voice, data, and video.”
I don’t understand what 3GIO has to do with ‘tomorrow networks’
because
3GIO is an replacement for the parallel PCI bus with ~200 lines by
the
high speed serial bus 3GIO with ~8 lines.
3GIO works at chip and mother board level … so it has mainly to
do
with silcon and at best with the system BIOS.
Any idea what QNX can do at this level??
How could QNX extend the performance of the 3GIO architecture ??
I have no clue …
Regards
Armin