Change resolution on daytona borad.

Guys,

I’m using QNX 6.1.0A on Daytona Board(XScale).
There is ‘devg-cotulla.so’ for graphics drivers.
Our daytona has 640 X 350 LCD screen.
And ‘cotulla.conf’ describe our screen properties like below.

I want to know how I can change screen to other resolution mode. (ex more
smaller resolution.)
Can I do it though changing contulla.conf ?
If so, is there anyone who teach me how I can ?

If not, Should I change ‘devg-cotulla’ driver ?
‘devg-cotulla.so’ is included in Xcale BSP on prebuilt binary.
Where I get the source code of ‘devg-cotulla.so’ ?

Any idea ?

YongSung


File ‘cotulla.conf’.

devg-cotulla.so parameters for tailoring to specific boards and display

modes.

hsw Horizontal Sync Width

elw End-of-line pixel clock wait

blw Beginning-of-line pixel clock wait

vsw Vertical sync pulse width

efw End-of-frame line clock wait count

bfw Beginning-of-frame line clock wait count

vsp Vertical Sync Polarity (0 = active high, 1 = active low)

hsp Horizontal Sync Polarity (0 = active high, 1 = active low)

pcp Pixel Clock Polarity (0 = data sampled on rising edge of L_PCLK, 1

=data sampled on falling edge)

oep Output enable polarity (0 - L_BIAS pin is active high in display mode

and parallel data input mode)

acb AC bias pin frequency

pcd Pixel Clock Divisor

type 1 = Active Display 0 = Passive Display

num 0 = Single Panel 1 = Dual Panel

board 0 = Daytona 1 = Lubbock

x width of panel

y height of panel

The driver will use the first un-commented entry.


\

Lubbock board, dual panel, passive display

#hsw=30,elw=7,blw=107,vsw=1,efw=0,bfw=0,vsp=0,hsp=0,pcp=1,oep=0,acb=0,pcd=9,
type=0,num=1,board=1,x=640,y=480

Daytona board, single panel, active display

hsw=30,elw=15,blw=73,vsw=1,efw=1,bfw=98,vsp=0,hsp=0,pcp=1,oep=0,acb=0,pcd=2,
type=1,num=0,board=0,x=640,y=350

As far as I know, the board only supports one resolution: 640x350x8.
The source to the driver is under NDA from Intel, so we are not allowed
to release it.

-Jay.

Previously, YongSung Yoon wrote in qdn.public.ddk.graphics:

Guys,

I’m using QNX 6.1.0A on Daytona Board(XScale).
There is ‘devg-cotulla.so’ for graphics drivers.
Our daytona has 640 X 350 LCD screen.
And ‘cotulla.conf’ describe our screen properties like below.

I want to know how I can change screen to other resolution mode. (ex more
smaller resolution.)
Can I do it though changing contulla.conf ?
If so, is there anyone who teach me how I can ?

If not, Should I change ‘devg-cotulla’ driver ?
‘devg-cotulla.so’ is included in Xcale BSP on prebuilt binary.
Where I get the source code of ‘devg-cotulla.so’ ?

Any idea ?

YongSung


File ‘cotulla.conf’.

devg-cotulla.so parameters for tailoring to specific boards and display

modes.

hsw Horizontal Sync Width

elw End-of-line pixel clock wait

blw Beginning-of-line pixel clock wait

vsw Vertical sync pulse width

efw End-of-frame line clock wait count

bfw Beginning-of-frame line clock wait count

vsp Vertical Sync Polarity (0 = active high, 1 = active low)

hsp Horizontal Sync Polarity (0 = active high, 1 = active low)

pcp Pixel Clock Polarity (0 = data sampled on rising edge of L_PCLK, 1

=data sampled on falling edge)

oep Output enable polarity (0 - L_BIAS pin is active high in display mode

and parallel data input mode)

acb AC bias pin frequency

pcd Pixel Clock Divisor

type 1 = Active Display 0 = Passive Display

num 0 = Single Panel 1 = Dual Panel

board 0 = Daytona 1 = Lubbock

x width of panel

y height of panel

The driver will use the first un-commented entry.


\

Lubbock board, dual panel, passive display

#hsw=30,elw=7,blw=107,vsw=1,efw=0,bfw=0,vsp=0,hsp=0,pcp=1,oep=0,acb=0,pcd=9,
type=0,num=1,board=1,x=640,y=480

Daytona board, single panel, active display

hsw=30,elw=15,blw=73,vsw=1,efw=1,bfw=98,vsp=0,hsp=0,pcp=1,oep=0,acb=0,pcd=2,
type=1,num=0,board=0,x=640,y=350


\


-Jay.

YongSung Yoon <yongsung@kr.ibm.com> wrote:

Guys,

I’m using QNX 6.1.0A on Daytona Board(XScale).
There is ‘devg-cotulla.so’ for graphics drivers.
Our daytona has 640 X 350 LCD screen.
And ‘cotulla.conf’ describe our screen properties like below.

I want to know how I can change screen to other resolution mode. (ex more
smaller resolution.)
Can I do it though changing contulla.conf ?
If so, is there anyone who teach me how I can ?

If not, Should I change ‘devg-cotulla’ driver ?
‘devg-cotulla.so’ is included in Xcale BSP on prebuilt binary.
Where I get the source code of ‘devg-cotulla.so’ ?

LCD screens, unlike monitors, do not support more than one resolution.
(Some more expensive panels support multiple resolutions by stretching
the image to the panels native resolution. Also, some high-end
graphics chips can pre-scale the image to the panels native resolution).

I assume you have the Daytona working already at 640x350…

While you can’t change the resolution as such, you could reduce the size
of the image, but this would introduce black borders around the edges.

If you want to reduce the image size in this manner, let us know, and
we can provide you with more details.

Dave

Any idea ?

YongSung



File ‘cotulla.conf’.

devg-cotulla.so parameters for tailoring to specific boards and display

modes.

hsw Horizontal Sync Width

elw End-of-line pixel clock wait

blw Beginning-of-line pixel clock wait

vsw Vertical sync pulse width

efw End-of-frame line clock wait count

bfw Beginning-of-frame line clock wait count

vsp Vertical Sync Polarity (0 = active high, 1 = active low)

hsp Horizontal Sync Polarity (0 = active high, 1 = active low)

pcp Pixel Clock Polarity (0 = data sampled on rising edge of L_PCLK, 1

=data sampled on falling edge)

oep Output enable polarity (0 - L_BIAS pin is active high in display mode

and parallel data input mode)

acb AC bias pin frequency

pcd Pixel Clock Divisor

type 1 = Active Display 0 = Passive Display

num 0 = Single Panel 1 = Dual Panel

board 0 = Daytona 1 = Lubbock

x width of panel

y height of panel

The driver will use the first un-commented entry.



Lubbock board, dual panel, passive display

#hsw=30,elw=7,blw=107,vsw=1,efw=0,bfw=0,vsp=0,hsp=0,pcp=1,oep=0,acb=0,pcd=9,
type=0,num=1,board=1,x=640,y=480

Daytona board, single panel, active display

hsw=30,elw=15,blw=73,vsw=1,efw=1,bfw=98,vsp=0,hsp=0,pcp=1,oep=0,acb=0,pcd=2,
type=1,num=0,board=0,x=640,y=350

While you can’t change the resolution as such, you could reduce the size
of the image, but this would introduce black borders around the edges.

If you want to reduce the image size in this manner, let us know, and
we can provide you with more details.

Yes.
I want to reduce the screen size despite of having black borders around the
edges.
Would you teach more details to me. ex) 320 * 128 or 320 * 175 .

Regards,

“David Donohoe” <ddonohoe@qnx.com> wrote in message
news:b28ght$chr$1@nntp.qnx.com

YongSung Yoon <> yongsung@kr.ibm.com> > wrote:
Guys,

I’m using QNX 6.1.0A on Daytona Board(XScale).
There is ‘devg-cotulla.so’ for graphics drivers.
Our daytona has 640 X 350 LCD screen.
And ‘cotulla.conf’ describe our screen properties like below.

I want to know how I can change screen to other resolution mode. (ex
more
smaller resolution.)
Can I do it though changing contulla.conf ?
If so, is there anyone who teach me how I can ?

If not, Should I change ‘devg-cotulla’ driver ?
‘devg-cotulla.so’ is included in Xcale BSP on prebuilt binary.
Where I get the source code of ‘devg-cotulla.so’ ?

LCD screens, unlike monitors, do not support more than one resolution.
(Some more expensive panels support multiple resolutions by stretching
the image to the panels native resolution. Also, some high-end
graphics chips can pre-scale the image to the panels native resolution).

I assume you have the Daytona working already at 640x350…

While you can’t change the resolution as such, you could reduce the size
of the image, but this would introduce black borders around the edges.

If you want to reduce the image size in this manner, let us know, and
we can provide you with more details.

Dave

Any idea ?

YongSung


File ‘cotulla.conf’.

devg-cotulla.so parameters for tailoring to specific boards and

display
modes.

hsw Horizontal Sync Width

elw End-of-line pixel clock wait

blw Beginning-of-line pixel clock wait

vsw Vertical sync pulse width

efw End-of-frame line clock wait count

bfw Beginning-of-frame line clock wait count

vsp Vertical Sync Polarity (0 = active high, 1 = active low)

hsp Horizontal Sync Polarity (0 = active high, 1 = active low)

pcp Pixel Clock Polarity (0 = data sampled on rising edge of L_PCLK,

1
=data sampled on falling edge)

oep Output enable polarity (0 - L_BIAS pin is active high in display

mode
and parallel data input mode)

acb AC bias pin frequency

pcd Pixel Clock Divisor

type 1 = Active Display 0 = Passive Display

num 0 = Single Panel 1 = Dual Panel

board 0 = Daytona 1 = Lubbock

x width of panel

y height of panel

The driver will use the first un-commented entry.


\

Lubbock board, dual panel, passive display

#hsw=30,elw=7,blw=107,vsw=1,efw=0,bfw=0,vsp=0,hsp=0,pcp=1,oep=0,acb=0,pcd=9,
type=0,num=1,board=1,x=640,y=480

Daytona board, single panel, active display

hsw=30,elw=15,blw=73,vsw=1,efw=1,bfw=98,vsp=0,hsp=0,pcp=1,oep=0,acb=0,pcd=2,
type=1,num=0,board=0,x=640,y=350
\

YongSung Yoon <yongsung@kr.ibm.com> wrote:
:> While you can’t change the resolution as such, you could reduce the size
:> of the image, but this would introduce black borders around the edges.
:>
:> If you want to reduce the image size in this manner, let us know, and
:> we can provide you with more details.

: Yes.
: I want to reduce the screen size despite of having black borders around the
: edges.
: Would you teach more details to me. ex) 320 * 128 or 320 * 175 .


You should be able to do this by simply modifying the ‘cotulla.conf’
file and the parameters passed to io-graphics.

If you haven’t already done so you should download the specifications
on the LCD controller and the LCD.

I found the LCD specs at:
http://www.sharpsma.com/pub/productfocus/publications/displays/
tft/auto/tec_specs_lq058t5drq1.pdf

The LCD controller specs can be found at the Intel website:
ftp://download.intel.com/design/pca/applicationsprocessors/
manuals/278522-001.pdf


You should look in particular at the following parameters in the
conf file: elw blw efw bfw x y

A quickly modified ‘cotulla.conf’ file for 320x128 may look something
like:

hsw=30,elw=200,blw=240,vsw=1,efw=120,bfw=200,vsp=0,hsp=0,pcp=1,oep=0,
acb=0,pcd=2,type=1,num=0,board=0,x=320,y=128

You could then start io-graphics:

io-graphics -dldevg-cotulla.so -amode=/etc/cotulla.conf -g320x128x8

(assuming you put your cotulla.conf in /etc)


Mike


: Regards,

: “David Donohoe” <ddonohoe@qnx.com> wrote in message
: news:b28ght$chr$1@nntp.qnx.com
:> YongSung Yoon <yongsung@kr.ibm.com> wrote:
:> > Guys,
:>
:> > I’m using QNX 6.1.0A on Daytona Board(XScale).
:> > There is ‘devg-cotulla.so’ for graphics drivers.
:> > Our daytona has 640 X 350 LCD screen.
:> > And ‘cotulla.conf’ describe our screen properties like below.
:>
:> > I want to know how I can change screen to other resolution mode. (ex
: more
:> > smaller resolution.)
:> > Can I do it though changing contulla.conf ?
:> > If so, is there anyone who teach me how I can ?
:>
:> > If not, Should I change ‘devg-cotulla’ driver ?
:> > ‘devg-cotulla.so’ is included in Xcale BSP on prebuilt binary.
:> > Where I get the source code of ‘devg-cotulla.so’ ?
:>
:> LCD screens, unlike monitors, do not support more than one resolution.
:> (Some more expensive panels support multiple resolutions by stretching
:> the image to the panels native resolution. Also, some high-end
:> graphics chips can pre-scale the image to the panels native resolution).
:>
:> I assume you have the Daytona working already at 640x350…
:>
:> While you can’t change the resolution as such, you could reduce the size
:> of the image, but this would introduce black borders around the edges.
:>
:> If you want to reduce the image size in this manner, let us know, and
:> we can provide you with more details.
:>
:> Dave
:>
:> > Any idea ?
:>
:> > YongSung
:>
:>
:> > File ‘cotulla.conf’.
:> > # devg-cotulla.so parameters for tailoring to specific boards and
: display
:> > modes.
:> > #
:> > # hsw Horizontal Sync Width
:> > # elw End-of-line pixel clock wait
:> > # blw Beginning-of-line pixel clock wait
:> > # vsw Vertical sync pulse width
:> > # efw End-of-frame line clock wait count
:> > # bfw Beginning-of-frame line clock wait count
:> > # vsp Vertical Sync Polarity (0 = active high, 1 = active low)
:> > # hsp Horizontal Sync Polarity (0 = active high, 1 = active low)
:> > # pcp Pixel Clock Polarity (0 = data sampled on rising edge of L_PCLK,
: 1
:> > =data sampled on falling edge)
:> > # oep Output enable polarity (0 - L_BIAS pin is active high in display
: mode
:> > and parallel data input mode)
:> > # acb AC bias pin frequency
:> > # pcd Pixel Clock Divisor
:> > # type 1 = Active Display 0 = Passive Display
:> > # num 0 = Single Panel 1 = Dual Panel
:> > # board 0 = Daytona 1 = Lubbock
:> > # x width of panel
:> > # y height of panel
:> > #
:> > # The driver will use the first un-commented entry.
:>
:>
:> > # Lubbock board, dual panel, passive display
:> >
: #hsw=30,elw=7,blw=107,vsw=1,efw=0,bfw=0,vsp=0,hsp=0,pcp=1,oep=0,acb=0,pcd=9,
:> > type=0,num=1,board=1,x=640,y=480
:>
:> > # Daytona board, single panel, active display
:> >
: hsw=30,elw=15,blw=73,vsw=1,efw=1,bfw=98,vsp=0,hsp=0,pcp=1,oep=0,acb=0,pcd=2,
:> > type=1,num=0,board=0,x=640,y=350
:>
:>
:>
:>

Thanks. It works.
But the color of our daytona LCD screen is something wrong when using 320 X
128 resolution.
White and yellow looks like pink or red.
Can I fix this problem by modifying ‘cotulla.conf’ ?
If so, could you teach me about this ?

YongSung,

“Michael Van Reenen” <mvr@qnx.com> wrote in message
news:b2brli$kp0$1@nntp.qnx.com

YongSung Yoon <> yongsung@kr.ibm.com> > wrote:
:> While you can’t change the resolution as such, you could reduce the
size
:> of the image, but this would introduce black borders around the edges.
:
:> If you want to reduce the image size in this manner, let us know, and
:> we can provide you with more details.

: Yes.
: I want to reduce the screen size despite of having black borders around
the
: edges.
: Would you teach more details to me. ex) 320 * 128 or 320 * 175 .


You should be able to do this by simply modifying the ‘cotulla.conf’
file and the parameters passed to io-graphics.

If you haven’t already done so you should download the specifications
on the LCD controller and the LCD.

I found the LCD specs at:
http://www.sharpsma.com/pub/productfocus/publications/displays/
tft/auto/tec_specs_lq058t5drq1.pdf

The LCD controller specs can be found at the Intel website:
ftp://download.intel.com/design/pca/applicationsprocessors/
manuals/278522-001.pdf


You should look in particular at the following parameters in the
conf file: elw blw efw bfw x y

A quickly modified ‘cotulla.conf’ file for 320x128 may look something
like:

hsw=30,elw=200,blw=240,vsw=1,efw=120,bfw=200,vsp=0,hsp=0,pcp=1,oep=0,
acb=0,pcd=2,type=1,num=0,board=0,x=320,y=128

You could then start io-graphics:

io-graphics -dldevg-cotulla.so -amode=/etc/cotulla.conf -g320x128x8

(assuming you put your cotulla.conf in /etc)


Mike


: Regards,

: “David Donohoe” <> ddonohoe@qnx.com> > wrote in message
: news:b28ght$chr$> 1@nntp.qnx.com> …
:> YongSung Yoon <> yongsung@kr.ibm.com> > wrote:
:> > Guys,
:
:> > I’m using QNX 6.1.0A on Daytona Board(XScale).
:> > There is ‘devg-cotulla.so’ for graphics drivers.
:> > Our daytona has 640 X 350 LCD screen.
:> > And ‘cotulla.conf’ describe our screen properties like below.
:
:> > I want to know how I can change screen to other resolution mode. (ex
: more
:> > smaller resolution.)
:> > Can I do it though changing contulla.conf ?
:> > If so, is there anyone who teach me how I can ?
:
:> > If not, Should I change ‘devg-cotulla’ driver ?
:> > ‘devg-cotulla.so’ is included in Xcale BSP on prebuilt binary.
:> > Where I get the source code of ‘devg-cotulla.so’ ?
:
:> LCD screens, unlike monitors, do not support more than one resolution.
:> (Some more expensive panels support multiple resolutions by stretching
:> the image to the panels native resolution. Also, some high-end
:> graphics chips can pre-scale the image to the panels native
resolution).
:
:> I assume you have the Daytona working already at 640x350…
:
:> While you can’t change the resolution as such, you could reduce the
size
:> of the image, but this would introduce black borders around the edges.
:
:> If you want to reduce the image size in this manner, let us know, and
:> we can provide you with more details.
:
:> Dave
:
:> > Any idea ?
:
:> > YongSung
:
:
:> > File ‘cotulla.conf’.
:> > # devg-cotulla.so parameters for tailoring to specific boards and
: display
:> > modes.
:> > #
:> > # hsw Horizontal Sync Width
:> > # elw End-of-line pixel clock wait
:> > # blw Beginning-of-line pixel clock wait
:> > # vsw Vertical sync pulse width
:> > # efw End-of-frame line clock wait count
:> > # bfw Beginning-of-frame line clock wait count
:> > # vsp Vertical Sync Polarity (0 = active high, 1 = active low)
:> > # hsp Horizontal Sync Polarity (0 = active high, 1 = active low)
:> > # pcp Pixel Clock Polarity (0 = data sampled on rising edge of
L_PCLK,
: 1
:> > =data sampled on falling edge)
:> > # oep Output enable polarity (0 - L_BIAS pin is active high in
display
: mode
:> > and parallel data input mode)
:> > # acb AC bias pin frequency
:> > # pcd Pixel Clock Divisor
:> > # type 1 = Active Display 0 = Passive Display
:> > # num 0 = Single Panel 1 = Dual Panel
:> > # board 0 = Daytona 1 = Lubbock
:> > # x width of panel
:> > # y height of panel
:> > #
:> > # The driver will use the first un-commented entry.
:
:
:> > # Lubbock board, dual panel, passive display
:
:
#hsw=30,elw=7,blw=107,vsw=1,efw=0,bfw=0,vsp=0,hsp=0,pcp=1,oep=0,acb=0,pcd=9,
:> > type=0,num=1,board=1,x=640,y=480
:
:> > # Daytona board, single panel, active display
:
:
hsw=30,elw=15,blw=73,vsw=1,efw=1,bfw=98,vsp=0,hsp=0,pcp=1,oep=0,acb=0,pcd=2,
:> > type=1,num=0,board=0,x=640,y=350
:
:
:
:

How are you starting io-graphics?

Can you post the command line used. Also can you post the parameters
you are using in ‘cotulla.conf’?

Thanks

Mike



YongSung Yoon <yongsung@kr.ibm.com> wrote:
: Thanks. It works.
: But the color of our daytona LCD screen is something wrong when using 320 X
: 128 resolution.
: White and yellow looks like pink or red.
: Can I fix this problem by modifying ‘cotulla.conf’ ?
: If so, could you teach me about this ?

: YongSung,

: “Michael Van Reenen” <mvr@qnx.com> wrote in message
: news:b2brli$kp0$1@nntp.qnx.com
:> YongSung Yoon <yongsung@kr.ibm.com> wrote:
:> :> While you can’t change the resolution as such, you could reduce the
: size
:> :> of the image, but this would introduce black borders around the edges.
:> :>
:> :> If you want to reduce the image size in this manner, let us know, and
:> :> we can provide you with more details.
:>
:> : Yes.
:> : I want to reduce the screen size despite of having black borders around
: the
:> : edges.
:> : Would you teach more details to me. ex) 320 * 128 or 320 * 175 .
:>
:>
:> You should be able to do this by simply modifying the ‘cotulla.conf’
:> file and the parameters passed to io-graphics.
:>
:> If you haven’t already done so you should download the specifications
:> on the LCD controller and the LCD.
:>
:> I found the LCD specs at:
:> http://www.sharpsma.com/pub/productfocus/publications/displays/
:> tft/auto/tec_specs_lq058t5drq1.pdf
:>
:> The LCD controller specs can be found at the Intel website:
:> ftp://download.intel.com/design/pca/applicationsprocessors/
:> manuals/278522-001.pdf
:>
:>
:> You should look in particular at the following parameters in the
:> conf file: elw blw efw bfw x y
:>
:> A quickly modified ‘cotulla.conf’ file for 320x128 may look something
:> like:
:>
:> hsw=30,elw=200,blw=240,vsw=1,efw=120,bfw=200,vsp=0,hsp=0,pcp=1,oep=0,
:> acb=0,pcd=2,type=1,num=0,board=0,x=320,y=128
:>
:> You could then start io-graphics:
:>
:> io-graphics -dldevg-cotulla.so -amode=/etc/cotulla.conf -g320x128x8
:>
:> (assuming you put your cotulla.conf in /etc)
:>
:>
:> Mike
:>
:>
:> : Regards,
:>
:> : “David Donohoe” <ddonohoe@qnx.com> wrote in message
:> : news:b28ght$chr$1@nntp.qnx.com
:> :> YongSung Yoon <yongsung@kr.ibm.com> wrote:
:> :> > Guys,
:> :>
:> :> > I’m using QNX 6.1.0A on Daytona Board(XScale).
:> :> > There is ‘devg-cotulla.so’ for graphics drivers.
:> :> > Our daytona has 640 X 350 LCD screen.
:> :> > And ‘cotulla.conf’ describe our screen properties like below.
:> :>
:> :> > I want to know how I can change screen to other resolution mode. (ex
:> : more
:> :> > smaller resolution.)
:> :> > Can I do it though changing contulla.conf ?
:> :> > If so, is there anyone who teach me how I can ?
:> :>
:> :> > If not, Should I change ‘devg-cotulla’ driver ?
:> :> > ‘devg-cotulla.so’ is included in Xcale BSP on prebuilt binary.
:> :> > Where I get the source code of ‘devg-cotulla.so’ ?
:> :>
:> :> LCD screens, unlike monitors, do not support more than one resolution.
:> :> (Some more expensive panels support multiple resolutions by stretching
:> :> the image to the panels native resolution. Also, some high-end
:> :> graphics chips can pre-scale the image to the panels native
: resolution).
:> :>
:> :> I assume you have the Daytona working already at 640x350…
:> :>
:> :> While you can’t change the resolution as such, you could reduce the
: size
:> :> of the image, but this would introduce black borders around the edges.
:> :>
:> :> If you want to reduce the image size in this manner, let us know, and
:> :> we can provide you with more details.
:> :>
:> :> Dave
:> :>
:> :> > Any idea ?
:> :>
:> :> > YongSung
:> :>
:> :>
:> :> > File ‘cotulla.conf’.
:> :> > # devg-cotulla.so parameters for tailoring to specific boards and
:> : display
:> :> > modes.
:> :> > #
:> :> > # hsw Horizontal Sync Width
:> :> > # elw End-of-line pixel clock wait
:> :> > # blw Beginning-of-line pixel clock wait
:> :> > # vsw Vertical sync pulse width
:> :> > # efw End-of-frame line clock wait count
:> :> > # bfw Beginning-of-frame line clock wait count
:> :> > # vsp Vertical Sync Polarity (0 = active high, 1 = active low)
:> :> > # hsp Horizontal Sync Polarity (0 = active high, 1 = active low)
:> :> > # pcp Pixel Clock Polarity (0 = data sampled on rising edge of
: L_PCLK,
:> : 1
:> :> > =data sampled on falling edge)
:> :> > # oep Output enable polarity (0 - L_BIAS pin is active high in
: display
:> : mode
:> :> > and parallel data input mode)
:> :> > # acb AC bias pin frequency
:> :> > # pcd Pixel Clock Divisor
:> :> > # type 1 = Active Display 0 = Passive Display
:> :> > # num 0 = Single Panel 1 = Dual Panel
:> :> > # board 0 = Daytona 1 = Lubbock
:> :> > # x width of panel
:> :> > # y height of panel
:> :> > #
:> :> > # The driver will use the first un-commented entry.
:> :>
:> :>
:> :> > # Lubbock board, dual panel, passive display
:> :> >
:> :
: #hsw=30,elw=7,blw=107,vsw=1,efw=0,bfw=0,vsp=0,hsp=0,pcp=1,oep=0,acb=0,pcd=9,
:> :> > type=0,num=1,board=1,x=640,y=480
:> :>
:> :> > # Daytona board, single panel, active display
:> :> >
:> :
: hsw=30,elw=15,blw=73,vsw=1,efw=1,bfw=98,vsp=0,hsp=0,pcp=1,oep=0,acb=0,pcd=2,
:> :> > type=1,num=0,board=0,x=640,y=350
:> :>
:> :>
:> :>
:> :>
:>
:>