Hi,
I am working on a device driver for a chip that is connected to the CPU
via PCI bus. I am wondering what all I need to do to intialize the PCI bus
for this device and what all the QNX PCI server already does for me? That
is, will automatically generate configuration cycles to enable memory
access, I/O access, parity detect etc.
Is there any documentation on what the PCI server acually does?
-Vinay
You have not mentioned what platform you are running on, but if it is an
x86 system, the BIOS should setup the I/O and memory regions for your chip.
If this is not happening, then when your application does a
‘pci_attach_device()’ function call, the PCI server will assign I/O ports
and memory regions and return these values to you in the pci_dev_info
structure.
The only case where this will not work, is if the chip is a bridge type
chip. Do you see any register values for your chip when you do a ‘pci -v’?
Previously, Vinay Ravuri wrote in qdn.public.ddk.network:
Hi,
I am working on a device driver for a chip that is connected to the CPU
via PCI bus. I am wondering what all I need to do to intialize the PCI bus
for this device and what all the QNX PCI server already does for me? That
is, will automatically generate configuration cycles to enable memory
access, I/O access, parity detect etc.Is there any documentation on what the PCI server acually does?
-Vinay
It will be on IBM 440GP processor (power pc core) - Don’t have the hardware
to run pci -v yet. How does pci_attach_device() know how much of PCI memory
to map and which IRQ to pick?
-Vinay
-Vinay
“Hugh Brown” <hsbrown@qnx.com> wrote in message
news:Voyager.030124082839.20696A@node90.ott.qnx.com…
You have not mentioned what platform you are running on, but if it is an
x86 system, the BIOS should setup the I/O and memory regions for your
chip.
If this is not happening, then when your application does a
‘pci_attach_device()’ function call, the PCI server will assign I/O ports
and memory regions and return these values to you in the pci_dev_info
structure.The only case where this will not work, is if the chip is a bridge type
chip. Do you see any register values for your chip when you do a ‘pci -v’?Previously, Vinay Ravuri wrote in qdn.public.ddk.network:
Hi,I am working on a device driver for a chip that is connected to the
CPU
via PCI bus. I am wondering what all I need to do to intialize the PCI
bus
for this device and what all the QNX PCI server already does for me?
That
is, will automatically generate configuration cycles to enable memory
access, I/O access, parity detect etc.Is there any documentation on what the PCI server acually does?
-Vinay
\
Previously, Vinay Ravuri wrote in qdn.public.ddk.network:
It will be on IBM 440GP processor (power pc core) - Don’t have the hardware
to run pci -v yet. How does pci_attach_device() know how much of PCI memory
to map and which IRQ to pick?
The PCI server automatically determines the sizes of the ioport and memory
and allocates the necessary resources to the device. The IRQ is determined
by the low-level server code and is platform specific.
-Vinay
-Vinay
“Hugh Brown” <> hsbrown@qnx.com> > wrote in message
news:> Voyager.030124082839.20696A@node90.ott.qnx.com> …
You have not mentioned what platform you are running on, but if it is an
x86 system, the BIOS should setup the I/O and memory regions for your
chip.
If this is not happening, then when your application does a
‘pci_attach_device()’ function call, the PCI server will assign I/O ports
and memory regions and return these values to you in the pci_dev_info
structure.The only case where this will not work, is if the chip is a bridge type
chip. Do you see any register values for your chip when you do a ‘pci -v’?Previously, Vinay Ravuri wrote in qdn.public.ddk.network:
Hi,I am working on a device driver for a chip that is connected to the
CPU
via PCI bus. I am wondering what all I need to do to intialize the PCI
bus
for this device and what all the QNX PCI server already does for me?
That
is, will automatically generate configuration cycles to enable memory
access, I/O access, parity detect etc.Is there any documentation on what the PCI server acually does?
-Vinay
\