Tomas Högström <tomas@scandicraft.se> wrote in article <3D09C785.9BAB78F6@scandicraft.se>…
Tomas,
Actually it does not matter. Which DMA mode they intend to use. Is it single transfer mode? In
this
case you really will have transfer of ONE byte per DMA cycle. But it doesn’t touch you. It’s
background hardware process without any intervension of CPU. During DMA cycle one byte written
into
RAM, but you have nothing to do with this. DMA controller has DMA transfer counter, every time
when
DMA cycle occurs it decreases. When this counter reach 0xffff (in other words - DMA controller
recievs the last byte in transfer, or it’s writting the last byte into memory buffer), the DMA
controller sets DACK (dma acknowledge) and TC (transfer complete or Terminal Count) signals.
Does
the card use these signals to set interrupt request on line?
In this asumption you have 4*byterates time to reprogram DMA controller. During reprogramming,
when
DMA is disabled, input bytes will just collect into FIFO and as soon as you enable DMA the card
sends these bytes to your new buffer.
Yes, but since the byterate is high this will use much of the CPU during the burst.
Did I miss something? When card intends to pass byte to memory, it sends hardware signal DREQx (dma
channel x request). DMA controller gets this signal and sends signal HRQ (hold request) in order to
take bus in monopolic usage, CPU answers HLDA (hold acknowledge), then DMA controller answers DACKx
(dma chan x acknowledge) to the board. CPU’s buses are in hiZ state. I.E. CPU has nothing to do
with DMA, it just stops in ISA architecture. Yes, it takes a bit of time, in other words it takes
few ISA bus cycles to write byte from card to system memory. For example, for worse case it takes 8
ISA clks for byte transfer. It takes 8 / (33 MHz) = 0.24 uS. It can be faster and it depends on
your hardware (PCI-to-ISA bridge, etc.)
Using 1 or 4 byte transfers,
When you program DMA controller, you tell him the start address of your buffer and lenght of
buffer, i.e. how many bytes you want to write, before to wake up your card by TC signal in order to
get interrupt. lenght of DMA buffer in 1 or 4 bytes is nonsense. But card might be designed to send
4 or more bytes per an ISA bus hold. Anyway the TC signal will generated only when buffer is full.
Just in this case, CPU has ocassion to idle a bit more time while DMA controller writes bytes to
memory. What is diference for you will data in buffer grow up on 1 byte or 4? You have only
programm 8237 chip differently and perhaps to have buffer lenght divisible without remainder by 4
for second case.
each transfer will take 7.5 or 30 microseconds
and after each transfer the CPU will get an interrupt and have to reprogram the
DMA controller?
If you will program the DMA controller to write into memory 4 bytes lenght buffer then yes. But
main idea in DMA is to use longer buffer, says 48 K bytes and let hardware to fill out this buffer
without any your intervention. So, it’s designed to get interrupt every 7.5481024 uS, just an
example for your case.
I’d recommend you to take a look at your PC/104 user manual. Many manufacturers include the section
“DMA operation”. Or just look at Intel 8237A datasheet. Intel’s “Peripheral Components” book
describes this chip very well.
Eduard.
ed1k at ukr dot net
Due to overhead there will probably not be so much time left between
the interrupt handlings during the 241 microsec bursts, will it?
400 such bursts per second → 100ms per second spent moving data or
reprogramming the DMA controller. This might be a problem or not depending on one’s
requirements.
Cheers / Tom
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