problem with IPL(Assabet like board)

Hi all,

I am working on an assabet like board on which I have already ported linux.
Now I am trying to port QNX 6.2 on to it.

So I have changed the timings in _start.S and changed the serial output
port to 3.
But I didn’t get any output . Then I put the same code which I used in
blob(Linux boot loader)
and tried to get the output(ie, couple of b’s).
But could not able to see any characters… then I uncommented last two
lines and put it in
a loop then it started printing ‘b’ as well as ‘c’.(If compile in Linux
ie, blob it is working
with/without loop)

Why is it happening like this.
Please find the source of _start.S I am using (As in Blob)

#include <arm/sa1100.h>

#define SER_BASE 0x80050000
.align 2
.globl _start

ldr r0,=SA1100_INTR_BASE
mov r1, #0x00
str r1, [r0, #SA1100_ICMR]

/* switch CPU to correct speed /
ldr r0, =SA1100_POWER_BASE
mov r1, #SA1100_PPCR_206_4
str r1, [r0, #SA1100_PPCR]
initalize serial port (UART 3) /
bl ser_init
bl memsetup

  • Check reason for reset and clear status bits
    ldr r0, =SA1100_RESET_BASE
    ldr r1, [r0, #SA1100_RCSR]
    and r1, r1, #0xf
    teq r1,#0x08
    bne normal_boot

/* yes, a wake-up. clear RCSR by writing a 1 */
mov r1, #0x08
str r1, [r0, #SA1100_RCSR] ;

/* get the value from the PSPR and jump to it */
ldr r0, =SA1100_POWER_BASE
ldr r1, [r0, #SA1100_PSPR]
mov pc, r1

/* enable I-cache */
mrc p15, 0, r1, c1, c0, 0 @ read control reg
orr r1, r1, #0x1000 @ set Icache
mcr p15, 0, r1, c1, c0, 0 @ write it back

b debug
ldr r0,=SER_BASE

check: ldr r1,[r0,#SA1100_UTSR1]
and r1,r1,#0x01
teq r1,#0x01
beq check

mov r1,#0x00
str r1,[r0,#SA1100_UTCR3]

mov r1,#0xff
str r1,[r0,#SA1100_UTSR0]

mov r1,#0x08
str r1,[r0,#SA1100_UTCR0]

mov r1,#0x00
str r1,[r0,#SA1100_UTCR1]

mov r1,#0x17
str r1,[r0,#SA1100_UTCR2]

mov r1,#0x03
str r1,[r0,#SA1100_UTCR3]

mov pc,lr

  • Initialise the memory controller
    ldr r0, =SA1110_MEM_BASE

ldr r1, MDCAS00_VAL
str r1, [r0, #SA1110_MDCAS00]

ldr r1, MDCAS01_VAL
str r1, [r0, #SA1110_MDCAS01]

ldr r1, MDCAS02_VAL
str r1, [r0, #SA1110_MDCAS02]

ldr r1, MDREFR_VAL
str r1, [r0, #SA1110_MDREFR]

str r1, [r0, #SA1110_MDCNFG]


  • Perform 8 reads from DRAM bank 0 to start self-refresh, then enable
    mov r2, #0xc0000000
    ldr r1, [r2]
    ldr r1, [r2]
    ldr r1, [r2]
    ldr r1, [r2]
    ldr r1, [r2]
    ldr r1, [r2]
    ldr r1, [r2]
    ldr r1, [r2]

    ldr r1, MDCNFG_ENABLED
    str r1, [r0, #SA1110_MDCNFG]

ldr r1, MSC0_VAL
str r1, [r0, #SA1110_MSC0]

ldr r1, MSC1_VAL
str r1, [r0, #SA1110_MSC1]

ldr r1, MSC2_VAL
str r1, [r0, #SA1110_MSC2]

ldr r1, MECR_VAL
str r1, [r0, #SA1110_MECR]

ldr r1, SMCNFG_VAL
str r1, [r0, #SA1110_SMCNFG]

mov pc,lr

bl main
b _start


  • Memory controller register values


MDCAS00_VAL: .word 0xaaaaaaa7
MDCAS01_VAL: .word 0xaaaaaaaa
MDCAS02_VAL: .word 0xaaaaaaaa
MDCAS20_VAL: .word 0xaaaaaa7f // 51MHz memory clock
MDCAS21_VAL: .word 0xaaaaaaaa
MDCAS22_VAL: .word 0xaaaaaaaa

MSC0_VAL: .word 0xb354d47c //SPA
MSC1_VAL: .word 0xb354b354 //SPA
MSC2_VAL: .word 0xb355b354 //SPA

MECR_VAL: .word 0x994a994a //SPA
MDREFR_VAL: .word 0x00345121 //SPA
SMCNFG_VAL: .word 0x3070c040 //SPA
MDCNFG_DISABLED: .word 0x0000f334
MDCNFG_ENABLED: .word 0x0000f337

/* For printing letter b */
ldr r0,=SER_BASE
mov r1,#0x62
2: mov r2,#0x10

1: str r1,[r0,#UTDR]
subs r2,r2,#1
bne 1b
// Uncomment the following lines to run it in loop
// eor r1,r1,#1
// b 2b