I’m a little unclear on who sets whether each interrupt line coming into the
PIC is edge or level triggered. Is it QNX, or does the BIOS do this?
In either case, am I right in assuming that all PCI interrupt lines should
be level triggered?
– Carl
Carl Morris <carl.morris@teranex.com> wrote:
I’m a little unclear on who sets whether each interrupt line coming into the
PIC is edge or level triggered. Is it QNX, or does the BIOS do this?In either case, am I right in assuming that all PCI interrupt lines should
be level triggered?
All PCI will operate as level triggered, all ISA/EISA will operate as
edge triggered.
QNX Training Services
http://www.qnx.com/support/training/
Please followup in this newsgroup if you have further questions.
David Gibbs wrote:
All PCI will operate as level triggered, all ISA/EISA
will operate as edge triggered.
Great, at least I understand that part correctly. Is it the job of the BIOS
to set each input line of the PIC for edge or level triggering, or a QNX
job?
– Carl
Carl Morris <carl.morris@teranex.com> wrote:
David Gibbs wrote:
All PCI will operate as level triggered, all ISA/EISA
will operate as edge triggered.Great, at least I understand that part correctly. Is it the job of the BIOS
to set each input line of the PIC for edge or level triggering, or a QNX
job?
I’m pretty sure it’s the job of the hardware – BIOS/PCI bridge/someone to do
this, not QNX.
QNX Training Services
http://www.qnx.com/support/training/
Please followup in this newsgroup if you have further questions.