Seems there is a little bug in the pci utility (QNX 6.2.1 and earlier).
When it reports state of command register with -vv verbosity level it
wrongly reports bitwise device control information. For example,
Command Reg = 41h
I/O space access enabled
…
Parity Checking disabled
Data/Address stepping enabled
It is wrong, should be
I/O space access enabled
…
Parity Checking enabled
Data/Address stepping disabled.
Also, it’s observed there is some bit shift for every bit more
significant than D6. For example,
Command Reg = 107h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Should be
…
SERR# driver enabled
Fast back-to-back transactions to different agents disabled.
Might be the bug also affects less significant bits like D3:D5, but I
didn’t have ocassion to check this out.
And last, I’m slightly disagree with term “Parity Checking
enabled/disabled”. Concerning the meaning of bit D6 of the command
register, it is completely wrong. All PCI devices MUST check parity
except only few of them, see p. 3.7.5 of PCI local bus specification
version 2.2 for details. What bit D6 means is the behaviour while
reporting of the detected parity errors. Therefore, in the PCI
specification, this bit is called “Parity Error Response” and I don’t
see any reason to change this term. Is there any?
Seems there is a little bug in the pci utility (QNX 6.2.1 and earlier).
When it reports state of command register with -vv verbosity level it
wrongly reports bitwise device control information. For example,
Command Reg = 41h
I/O space access enabled
…
Parity Checking disabled
Data/Address stepping enabled
It is wrong, should be
I/O space access enabled
…
Parity Checking enabled
Data/Address stepping disabled.
Also, it’s observed there is some bit shift for every bit more
significant than D6. For example,
Command Reg = 107h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Checking disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents enabled
Should be
…
SERR# driver enabled
Fast back-to-back transactions to different agents disabled.
Might be the bug also affects less significant bits like D3:D5, but I
didn’t have ocassion to check this out.
And last, I’m slightly disagree with term “Parity Checking
enabled/disabled”. Concerning the meaning of bit D6 of the command
register, it is completely wrong. All PCI devices MUST check parity
except only few of them, see p. 3.7.5 of PCI local bus specification
version 2.2 for details. What bit D6 means is the behaviour while
reporting of the detected parity errors. Therefore, in the PCI
specification, this bit is called “Parity Error Response” and I don’t
see any reason to change this term. Is there any?
Yes there is a bug in the pci utility. Thanks for pointing this out,
No problem.
I will fix it up.
Thank you a lot.
Cheers,
Eduard.
P.S. Yesterday I run across the “pci.h” file somewhere under
/usr/include and all definitions there look OK, so probably that utility
doesn’t use those definitions or use them in a wrong way.