In article <firstname.lastname@example.org>, motih <email@example.com> wrote:
I’m currently working on a startup code for my BCM1250 based board.
looking at the bsp for BCM1250 I see that the qtime implementation does not
use the internal cont-compare
MIPS64 standard registers but rather a BCM private timer.
What is the motivation behind this implementation ? why not using the
standard count-compare scheme ?
Due to some sillyness in the CPU architecture of putting both the
IM0-7 and IE bits in the CP0 STATUS register with no way of atomically
changing them, an SMP system does not allow programs to directly attach
to any of the top level interrupt lines (the ones controlled by
the IM0-7 bits). We can’t keep the IM0-7 bits in sync across the
multiple CPU’s as they’re masked and unmasked. Devices must be
attached to another interrupt controller that eventually cascades
in to one of the top level interrupt lines.
Since the COUNT/COMPARE interrupt ties directly to one of the top
level interrupts, it’s not allowed to be used in an SMP system.
Some other timer hardware has to be used to provide the clock tick.
Brian Stecher (firstname.lastname@example.org) QNX Software Systems, Ltd.
phone: +1 (613) 591-0931 (voice) 175 Terence Matthews Cr.
+1 (613) 591-3579 (fax) Kanata, Ontario, Canada K2M 1W8