GPIO Ports

Hi,

I am working with QNX 6.3 on MPC Lite5200.
I want to use some GPIO Pins. So I have to
configurate a port. I want to use PSC3 for
GPIO. So I have to write in the GPS Port
Configuration Register (MBAR+0xB00). First
of all I tried to read this register with the
following code:

#include <stdio.h>
#include <inttypes.h>
#include <sys/neutrino.h>
#define GPSPCR 0x80000B00;
int main(int anz,char **args)
{
volatile uint32_t inhalt;
inhalt=*(volatile uint32_t *) GPSPCR;
printf("%X\n",inhalt);
return 0;
}

On my MPC I get:

./gpio

Process 778248 (gpio) terminated SIGSEGV code=1 fltno=11 ip=48040474
ref=80000b0
0
Memory fault

What is the problem. I think MCP is a memory mapped architekture, so I
dont have to use ThreadCtl(), mmap_device_io() and in32() like on
x86?

Thanks, Stephan

sh263 <stephan.huels@bms-dot-de.no-spam.invalid> wrote:

Hi,

I am working with QNX 6.3 on MPC Lite5200.
I want to use some GPIO Pins. So I have to
configurate a port. I want to use PSC3 for
GPIO. So I have to write in the GPS Port
Configuration Register (MBAR+0xB00). First
of all I tried to read this register with the
following code:

#include <stdio.h
#include <inttypes.h
#include <sys/neutrino.h
#define GPSPCR 0x80000B00;
int main(int anz,char **args)
{
volatile uint32_t inhalt;
inhalt=*(volatile uint32_t *) GPSPCR;
printf("%X\n",inhalt);
return 0;
}

On my MPC I get:

./gpio

Process 778248 (gpio) terminated SIGSEGV code=1 fltno=11 ip=48040474
ref=80000b0
0
Memory fault

What is the problem. I think MCP is a memory mapped architekture, so I
dont have to use ThreadCtl(), mmap_device_io() and in32() like on
x86?

No, you must still use:

ThreadCtl(_NTO_TCTL_IO, 0);

and also, you must use either the mmap_device_memory() or mmap_device_io()
calls to get a pointer to the registers you wish to modify.


Thanks, Stephan

David Green (dgreen@qnx.com)
QNX Software Systems Ltd.
http://www.qnx.com

Hi David,

thanks for your help. I see I have to use the functions for io mapped
architektures. I tried some addreses and I think 0xF0000000 ist the
base addres not 0x80000000. Probably the bsp change this default
address.

Regards Stephan

int main(int anz,char **args)
{
uintptr_t handle;
volatile uint32_t inhalt;
if(ThreadCtl(_NTO_TCTL_IO,0)==-1) printf(“Rechte nicht
vorhanden…\n”);
handle=mmap_device_io(0x04,0xF0000B00);
inhalt=in32(handle);
printf("%X\n",inhalt);
return 0;
}

sh263 <stephan.huels@bms-dot-de.no-spam.invalid> wrote:

Hi David,

thanks for your help. I see I have to use the functions for io mapped
architektures. I tried some addreses and I think 0xF0000000 ist the
base addres not 0x80000000. Probably the bsp change this default
address.

Regards Stephan

int main(int anz,char **args)
{
uintptr_t handle;
volatile uint32_t inhalt;
if(ThreadCtl(_NTO_TCTL_IO,0)==-1) printf(“Rechte nicht
vorhanden…\n”);
handle=mmap_device_io(0x04,0xF0000B00);
inhalt=in32(handle);
printf("%X\n",inhalt);
return 0;
}

Yes, the MGT5200 BSP moves the on-chip register base to 0xf0000000.

David Green (dgreen@qnx.com)
QNX Software Systems Ltd.
http://www.qnx.com

Hi David,

ok thanks for your help.

Regards, Stephan