APIC

Is using APIC under QNX4 a case of contact sales rep? Or is this something
a normal human can do on its own.

  • Mario

Mario Charest wrote:

Is using APIC under QNX4 a case of contact sales rep? Or is this something
a normal human can do on its own.

Depends what you want to use the APIC for/more details on what you’re
wanting to do.

Cheers,
Adam

QNX Software Systems Ltd.
[ amallory@qnx.com ]

With a PC, I always felt limited by the software available.
On Unix, I am limited only by my knowledge.
–Peter J. Schoenster <pschon@baste.magibox.net>

“Adam Mallory” <amallory@qnx.com> wrote in message
news:c97q0u$ecb$1@inn.qnx.com

Mario Charest wrote:

Is using APIC under QNX4 a case of contact sales rep? Or is this
something
a normal human can do on its own.

Depends what you want to use the APIC for/more details on what you’re
wanting to do.

The whole issue is still unclear to me but appartlty some of the new
hardware we are looking at
only support APIC (maybe it’s a BIOS issue). I beleive the BIOS will
assigned PCI interrupt through APIC (interrupt 22 for example).


Cheers,
Adam

QNX Software Systems Ltd.
[ > amallory@qnx.com > ]

With a PC, I always felt limited by the software available.
On Unix, I am limited only by my knowledge.
–Peter J. Schoenster <> pschon@baste.magibox.net

Mario Charest wrote:

The whole issue is still unclear to me but appartlty some of the new
hardware we are looking at
only support APIC (maybe it’s a BIOS issue). I beleive the BIOS will
assigned PCI interrupt through APIC (interrupt 22 for example).

I don’t really understand how a piece of hardware would only support a
specific interrupt controller (why would it care, especially if it’s on
the PCI bus).

\

Cheers,
Adam

QNX Software Systems Ltd.
[ amallory@qnx.com ]

With a PC, I always felt limited by the software available.
On Unix, I am limited only by my knowledge.
–Peter J. Schoenster <pschon@baste.magibox.net>

“Adam Mallory” <amallory@qnx.com> wrote in message
news:c97seb$ge1$1@inn.qnx.com

Mario Charest wrote:

The whole issue is still unclear to me but appartlty some of the new
hardware we are looking at
only support APIC (maybe it’s a BIOS issue). I beleive the BIOS will
assigned PCI interrupt through APIC (interrupt 22 for example).

I don’t really understand how a piece of hardware would only support a
specific interrupt controller (why would it care, especially if it’s on
the PCI bus).

The hardware I’m talking about is the cpu card (SBC)

Cheers,
Adam

QNX Software Systems Ltd.
[ > amallory@qnx.com > ]

With a PC, I always felt limited by the software available.
On Unix, I am limited only by my knowledge.
–Peter J. Schoenster <> pschon@baste.magibox.net

Mario Charest wrote:

The hardware I’m talking about is the cpu card (SBC)

The APIC should have a lagacy mode which compresses the irq levels into
the old 0->15 I believe - are they saying this isn’t going to happen?

If not, then it’s not going to be straight forward. The handling of
hardware interrupts is done via irq0->15 in QNX4.

\

Cheers,
Adam

QNX Software Systems Ltd.
[ amallory@qnx.com ]

With a PC, I always felt limited by the software available.
On Unix, I am limited only by my knowledge.
–Peter J. Schoenster <pschon@baste.magibox.net>

“Adam Mallory” <amallory@qnx.com> wrote in message
news:c980c8$ja2$1@inn.qnx.com

Mario Charest wrote:

The hardware I’m talking about is the cpu card (SBC)

The APIC should have a lagacy mode which compresses the irq levels into
the old 0->15 I believe - are they saying this isn’t going to happen?

Yep I think that’s the case, legacy obliterated…

If not, then it’s not going to be straight forward. The handling of
hardware interrupts is done via irq0->15 in QNX4.

Since qnx_hint_attach supported >15 interrupt (for software interrupt) I
though there was a quantum of a chance.

Cheers,
Adam

QNX Software Systems Ltd.
[ > amallory@qnx.com > ]

With a PC, I always felt limited by the software available.
On Unix, I am limited only by my knowledge.
–Peter J. Schoenster <> pschon@baste.magibox.net

Mario Charest wrote:

Since qnx_hint_attach supported >15 interrupt (for software interrupt) I
though there was a quantum of a chance.

It does, but that vector doesn’t go through the HW interrupt path. One
issue I could see, is that the software interrupt path doesn’t make a
distinction between coming from user code, or coming from kernel code.
With HW interrupts, we take different courses of action depending if
we’re interrupting user code, or kernel code. With SW interrupt, the
assumption is that a SWI is called from user code always. On top of
that, QNX4 also assume that the PIC speaks “8259”, so if the legacy mode
is ripped out, I doubt much will work.

If the “speak 8259” was not an issue, (warning this could be considered
“crazy”) you could take the NMI example code from usr/free, and use it
as a base to stuff an entry into the IDT for the vector you want to
handle. Then in your handler, make a call to one of the HW interrupt
vectors, simulating a hardware interrupt for one of the well know vectors.

The reason you can’t/shouldn’t do it from one of the SWINT vectors is
the user code call assumption. More specifically, certain kernel
structures are assumed to be sane at SWI time, when in fact we got
asynchronously interrupted.

Just my $0.03 :slight_smile:

Cheers,
Adam

QNX Software Systems Ltd.
[ amallory@qnx.com ]

With a PC, I always felt limited by the software available.
On Unix, I am limited only by my knowledge.
–Peter J. Schoenster <pschon@baste.magibox.net>