Hello, All!
Could anyone enlighten me about the following question: Can I rely on TSC
synchronization between the two CPUs while running in the SMP mode at x86
arch ?
If yes, how is synchronization is done in QNX6 ?
How is large can be TSC dispersion between the CPUs ?
What will happen if I read the TSC from one of the CPUs via RDTSC and then
will read again TSC register but from another CPU and subtract first value
from the second value - do I will get the right time difference ?
Thanks !
With best regards, Mike Gorchak. E-mail: mike@malva.com.ua
“Mike Gorchak” <mike@malva.com.ua> wrote in message
news:dbnbm3$t4g$1@inn.qnx.com…
Hello, All!
Could anyone enlighten me about the following question: Can I rely on TSC
synchronization between the two CPUs while running in the SMP mode at x86
arch ?
If yes, how is synchronization is done in QNX6 ?
How is large can be TSC dispersion between the CPUs ?
What will happen if I read the TSC from one of the CPUs via RDTSC and then
will read again TSC register but from another CPU and subtract first value
from the second value - do I will get the right time difference ?
I would make an educated guess that this could work but not on all CPU
model, basicly it’s not portable. If CPU doesn’t have any throtleling that
can affect CPU clock you should be ok (using the diff).
That being said latest P4 have a new behavior that keeps the counter couting
at same frequency what ever the throttleing.
Thanks !
With best regards, Mike Gorchak. E-mail: > mike@malva.com.ua
Hello, Mario!
??>> Could anyone enlighten me about the following question: Can I rely on
??>> TSC synchronization between the two CPUs while running in the SMP mode
??>> at x86 arch ? If yes, how is synchronization is done in QNX6 ? How is
??>> large can be TSC dispersion between the CPUs ? What will happen if I
??>> read the TSC from one of the CPUs via RDTSC and then will read again
??>> TSC register but from another CPU and subtract first value from the
??>> second value - do I will get the right time difference ?
MC> I would make an educated guess that this could work but not on all CPU
MC> model, basicly it’s not portable. If CPU doesn’t have any throtleling
MC> that can affect CPU clock you should be ok (using the diff).
So anyway it would be nice to listen QSS clarification for this issue,
because they are introduced ClockCycles() function and many others which
rely on RDTSC command and TSC register on x86 platform without any
clarification and warnings while running SMP microkernel and as I can
understand other hardware platforms are using similar to TSC register
functionality too.
With best regards, Mike Gorchak. E-mail: mike@malva.com.ua
Hello, Mike!
MG> So anyway it would be nice to listen QSS clarification for this issue,
MG> because they are introduced ClockCycles() function and many others
MG> which rely on RDTSC command and TSC register on x86 platform without
MG> any clarification and warnings while running SMP microkernel and as I
MG> can understand other hardware platforms are using similar to TSC
MG> register functionality too.
Sorry, I’ve found a warning about the SMP and ClockCycles() in the docs.
With best regards, Mike Gorchak. E-mail: mike@malva.com.ua
Mike Gorchak wrote:
Sorry, I’ve found a warning about the SMP and ClockCycles() in the docs.
The docs are getting pretty good huh ? I am getting close to the point
where I am willing to say that QNX has the best docs in the business.
Kudos to the docs team.
Rennie
Rennie Allen <rnogspamallen@comcast.net> wrote:
Mike Gorchak wrote:
Sorry, I’ve found a warning about the SMP and ClockCycles() in the docs.
The docs are getting pretty good huh ? I am getting close to the point
where I am willing to say that QNX has the best docs in the business.
Kudos to the docs team.
Thanks, Rennie. I’ll pass your comments to the rest of the team.
\
Steve Reid stever@qnx.com
Technical Editor
QNX Software Systems