Jörg Hering schrieb:
[quote]Eugenio Yime schrieb:
Hi everybody,
I’m trying to port a Linux driver for my PC104 analog / digital - input /
output, however I can’t access memory address 0x000D:F000.
Here is a how the source code in LINUX access memory for my hardware :
.
.
.
spi_reg.control_reg = ioremap(MMCRBASE+SPI_CTRL_REG, 1);
.
.
.
Then I read AMD ELAN Manual and I see that MMCRBASE is an “alias” for
address 0xFFFE:F000 (MMCR register) and it points to address 0x000D:F000
(CBAR register value), where CBAR register is in address 0x0000:FFFC. Also
in AMD ELAN MANUAL is explained that MMCR registes has a size of 0xFFF bytes
and CBAR has 32 bit length.
I wrote a program to verify CBAR value wich is explicitly used in Linux
driver.
int main(int argc, char *argv[]) {
volatile uint32_t * CBAR;
volatile uint32_t value32;
/* Mapping CBAR */
CBAR = mmap(0, 4, PROT_READ | PROT_NOCACHE, MAP_BELOW16M |
MAP_PHYS | MAP_SHARED, NOFD, 0xFFFC);
if ( CBAR == MAP_FAILED ) {
printf(“mmap failed : %s\n”, strerror(errno));
return EXIT_FAILURE;
}
value32 = CBAR[0];
printf(“MMCR Alias Addres (CBAR Value) is 0x%04x \n”, value32);
mumap(CBAR, 4);
return EXIT_SUCESS;
}
Well CBAR always has a value of 0x800D:F000, in ELAN Manual is explained
that the first bit means if “alias” of MMCR is active, so this mean that
MMCR is “aliased” to address 0x000D:F000.
Again in my initial problem I decide to access the whole MMCR register for
testing spi and accessing spi registers.
Here is the code
int main(int argc, char *argv[]) {
volatile void * MMCR;
volatile uint8_t value8;
/* Mapping MMCR “alias address” */
MMCR = mmap(0, 0xFFF, PROT_READ | PROT_WRITE | PROT_NOCACHE,
MAP_BELOW16M |
MAP_PHYS | MAP_SHARED, NOFD, 0x0DF000);
if ( MMCR == MAP_FAILED ) {
printf(“mmap failed : %s\n”, strerror(errno));
return EXIT_FAILURE;
}
memcpy(&value8, MMCR + SPI_CTRL_REG, 1);
value8 =| CONTROL_BITS;
memcpy(MMCR + SPI_CTRL_REG, &value8, 1);
.
.
.
return EXIT_SUCESS;
}
However my program halts in the first memcpy …
Can anyone help me?
Thanks,
here my Code from the QNX4.2x World
sc520.c
#include <stdio.h
#include <fcntl.h
#include <stdlib.h
#include <unistd.h
#include <sys/mman.h
#include <hw/inout.h
#include “Sc520.h”
#include “io.h”
//---------------------------------------------------------------------------
static DWORD MMCR_base;
static BYTE *MMCR_addr;
//---------------------------------------------------------------------------
void initMMCRBase(void)
{
int fd;
FirstIO();
if(in8(CBAR+3)&0x80)
MMCR_base=in32(CBAR)&0x3fffffffL;
else
MMCR_base=MMCR_BASE_DEFAULT;
fd=shm_open(“Physical”,O_RDWR,0777);
MMCR_addr=mmap(0,4096,PROT_READ|PROT_WRITE,MAP_SHARED,fd,MMCR_base);
close(fd);
}
//---------------------------------------------------------------------------
BYTE rwMMCRByte(int rw,DWORD offset,BYTE value)
{
BYTE *tmp;
tmp=MMCR_addr+offset;
if(rw)
*tmp=value;
return(*tmp);
}
//---------------------------------------------------------------------------
WORD rwMMCRWord(int rw,DWORD offset,WORD value)
{
WORD *tmp;
tmp=(WORD *)(MMCR_addr+offset);
if(rw)
*tmp=value;
return(*tmp);
}
//---------------------------------------------------------------------------
DWORD rwMMCRDword(int rw,DWORD offset,DWORD value)
{
DWORD *tmp;
tmp=(DWORD *)(MMCR_addr+offset);
if(rw)
*tmp=value;
return(*tmp);
}
//---------------------------------------------------------------------------
and sc520.h
/******************************************************************************
- Elan SC520 microcontroller Generic Header File *
*****************************************************************************/
/******************************************************************************
-
Copyright 1999 Advanced Micro Devices, Inc.
-
-
This software is the property of Advanced Micro Devices, Inc (AMD)
which
-
specifically grants the user the right to modify, use and distribute
this
-
software provided this COPYRIGHT NOTICE is not removed or altered. All
-
other rights are reserved by AMD.
-
-
THE MATERIALS ARE PROVIDED “AS IS” WITHOUT ANY EXPRESS OR IMPLIED
WARRANTY
-
OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF
-
THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE.
-
IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES
WHATSOEVER
-
(INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
-
INTERRUPTION, LOSS OF INFORMAITON) ARISING OUT OF THE USE OF OR INABILITY
-
TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY OF
-
SUCH DAMAGES. BECAUSE SOME JURSIDICTIONS PROHIBIT THE EXCLUSION OR
-
LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE
ABOVE
-
LIMITATION MAY NOT APPLY TO YOU.
-
-
AMD does not assume any responsibility for any errors that may appear in
-
the Materials nor any responsibility to support or update the Materials.
-
AMD retains the right to make changes to its test specifications at any
-
time, without notice.
-
-
So that all may benefit from your experience, please report any
problems
-
or suggestions about this software back to AMD. Please include your
name,
-
company, telephone number, AMD product requiring support and
question or
-
problem encountered.
-
-
Advanced Micro Devices, Inc. Worldwide support and contact
-
Embedded Processor Division information available at:
-
Systems Engineering epd.support@amd.com
-
5204 E. Ben White Blvd. -or-
-
Austin, TX 78741
http://www.amd.com/html/support/techsup.html
-
==========================================================================*/
#include “types.h”
#define READ 0
#define WRITE 1
#define MMCR 0xdf000 /* Memory Mapped configuration Region Base
Address /
#define MMCR_BASE_DEFAULT 0xfffef000L / The default base address */
/******************************************************************************
- Am5x86 CPU Registers *
******************************************************************************/
#define OFFS_REVID 0x00 /* ElanSC520 Microcontroller Revision ID
Register /
#define OFFS_CPUCTL 0x02 / Am5x86 CPU Control Register */
#define REVID (MMCR + OFFS_REVID) /* ElanSC520 Microcontroller
Revision ID Register /
#define CPUCTL (MMCR + OFFS_CPUCTL) / Am5x86 CPU Control Register */
/* Am5x86 CPU Register Masks */
/*
REVID Register Bit Masks
*/
#define PRODUCT_ID 0x00F0 /* Product type of ElanSC520 ucontroller
Mask /
#define MAJORSTEP 0x00E0 / Major Stepping Level Mask /
#define MINORSTEP 0x0007 / Minor Stepping Level Mask */
/* CPUCTL Register Bit Definitions */
#define CACHE_WR_MODE 0x0010 /* Cache Write Mode Mask /
#define CPU_CLK_SPD_66 0x0000 / CPU Clock Speed 66Mhz Mask /
#define CPU_CLK_SPD_100 0x0001 / CPU Clock Speed 100Mhz Mask /
#define CPU_CLK_SPD_133 0x0002 / CPU Clock Speed 133Mhz Mask */
/*******************************
- SDRAM CONTROLLER REGISTERS *
*******************************/
#define OFFS_DRCCTL 0x0010 /* SDRAM Control Register /
#define OFFS_DRCTMCTL 0x0012 / SDRAM Timing Control Register /
#define OFFS_DRCCFG 0x0014 / SDRAM Bank Configuration Register*/
#define OFFS_DRCBENDADR 0x0018 /* SDRAM Bank 0-3 Ending Address
Register*/
#define OFFS_ECCCTL 0x0020 /* ECC Control Register /
#define OFFS_ECCSTA 0x0021 / ECC Status Register /
#define OFFS_ECCCKBPOS 0x0022 / ECC Check Bit Position Register /
#define OFSS_ECCKTEST 0x0023 / ECC Check Code Test Register /
#define OFFS_ECCSBADD 0x0024 / ECC Single-Bit Error Address Register /
#define OFSS_ECCMBADD 0x0028 / ECC Multi_Bit Error Address Register /
#define DRCCTL (MMCR + OFFS_DRCCTL) / SDRAM Control Register /
#define DRCTMCTL (MMCR + OFFS_DRCTMCTL) / SDRAM Timing Control Register /
#define DRCCFG (MMCR + OFFS_DRCCFG) / SDRAM Bank Configuration Register*/
#define DRCBENDADR (MMCR + OFFS_DRCBENDARD)/* SDRAM Bank 0-3 Ending
Address Register*/
#define ECCCTL (MMCR + OFFS_ECCCTL) /* ECC Control Register /
#define ECCSTA (MMCR + OFFS_ECCSTA) / ECC Status Register /
#define ECCCKBPOS (MMCR + OFFS_ECCCKBPOS) / ECC Check Bit Position
Register /
#define ECCKTEST (MMCR + OFFS_ECCKTEST) / ECC Check Code Test Register /
#define ECCSBADD (MMCR + OFFS_ECCSBADD) / ECC Single-Bit Error Address
Register /
#define ECCMBADD (MMCR + OFFS_ECCMBADD) / ECC Multi_Bit Error Address
Register /
/
SDRAM Controller Register Bit Definitions
*/
/* SDRAM Control Register Bit Definitions */
#define WB_TST_ENB 0x80 /* Write Buffer Test Mode Enable */
#define RFSH_SPD_7 0x00 /* DRAM Refresh Request Speed 7.8 us /
#define RFSH_SPD_15 0x10 / DRAM Refresh Request Speed 15.6 us /
#define RFSH_SPD_31 0x20 / DRAM Refresh Request Speed 31.2 us /
#define RFSH_SPD_62 0x30 / DRAM Refresh Request Speed 62.5 us */
#define RFSH_END 0x08 /* DRAM Refresh Enable */
#define OPMODE_SEL_NSM 0x00 /* SDRAM Operation MODE Select: Normal
SDRAM Mode /
#define OPMODE_SEL_NOP 0x01 / SDRAM Operation MODE Select: NOP
Command Enabled /
#define OPMODE_SEL_CTD_ABP 0x02 / SDRAM Operation MODE Select: CPU To
DRAM cycles converted to All Banks Precharge Commands /
#define OPMODE_SEL_CTD_LMR 0x03 / SDRAM Operation MODE Select: CPU To
DRAM cycles converted to a Load Mode Register command /
#define OPMODE_SEL_ARE 0x04 / SDRAM Operation MODE Select: Auto
Refresh Enabled */
/* SDRAM Timing Control Register Bit Definitions */
#define CAS_LAT 0x10 /* SDRAM /CAS Latency */
#define RAS_PCHG_DLY_2T 0x00 /* SDRAM RAS Precharge Latency: 2T /
#define RAS_PCHG_DLY_3T 0x04 / SDRAM RAS Precharge Latency: 3T /
#define RAS_PCHG_DLY_4T 0x08 / SDRAM RAS Precharge Latency: 4T
(default) /
#define RAS_PCHG_DLY_6T 0x0c / SDRAM RAS Precharge Latency: 6T */
#define RAS_CAS_DLY_2T 0x00 /* SDRAM RAS-to-CAS Delay: 2T /
#define RAS_CAS_DLY_3T 0x01 / SDRAM RAS-to-CAS Delay: 3T /
#define RAS_CAS_DLY_4T 0x02 / SDRAM RAS-to-CAS Delay: 4T(default) */
/* SDRAM Bank Configuration Register Bit Definitions */
#define BNK3_BNK_CNT 0x8000 /* Bank 3 Internal SDRAM Bank Count /
#define BNK3_COL_WDTH_8 0x0000 / Bank 3 Column Address Width : 8 bits /
#define BNK3_COL_WDTH_9 0x1000 / Bank 3 Column Address Width : 9 bits /
#define BNK3_COL_WDTH_10 0x2000 / Bank 3 Column Address Width : 10
bits /
#define BNK3_COL_WDTH_11 0x3000 / Bank 3 Column Address Width : 11
bits */
#define BNK2_BNK_CNT 0x0800 /* Bank 2 Internal SDRAM Bank Count /
#define BNK2_COL_WDTH_8 0x0000 / Bank 2 Column Address Width : 8 bits /
#define BNK2_COL_WDTH_9 0x0100 / Bank 2 Column Address Width : 9 bits /
#define BNK2_COL_WDTH_10 0x0200 / Bank 2 Column Address Width : 10
bits /
#define BNK2_COL_WDTH_11 0x0300 / Bank 2 Column Address Width : 11
bits */
#define BNK1_BNK_CNT 0x0080 /* Bank 1 Internal SDRAM Bank Count /
#define BNK1_COL_WDTH_8 0x0000 / Bank 1 Column Address Width : 8 bits /
#define BNK1_COL_WDTH_9 0x0010 / Bank 1 Column Address Width : 9 bits /
#define BNK1_COL_WDTH_10 0x0020 / Bank 1 Column Address Width : 10
bits /
#define BNK1_COL_WDTH_11 0x0030 / Bank 1 Column Address Width : 11
bits */
#define BNK0_BNK_CNT 0x0008 /* Bank 0 Internal SDRAM Bank Count /
#define BNK0_COL_WDTH_8 0x0000 / Bank 0 Column Address Width : 8 bits /
#define BNK0_COL_WDTH_9 0x0001 / Bank 0 Column Address Width : 9 bits /
#define BNK0_COL_WDTH_10 0x0002 / Bank 0 Column Address Width : 10
bits /
#define BNK0_COL_WDTH_11 0x0003 / Bank 0 Column Address Width : 11
bits */
/* SDRAM Bank 0-3 Ending Address Register Bit Definitions */
#define BNK3_ENB 0x80000000 /* Bank 3 Enable /
#define BNK2_ENB 0x00800000 / Bank 2 Enable /
#define BNK1_ENB 0x00008000 / Bank 1 Enable /
#define BNK0_ENB 0x00000080 / Bank 0 Enable */
/* SDRAM Bank 0-3 Ending Address Register masks */
#define BNK3_END 0x7F000000 /* Bank 3 Ending Address /
#define BNK2_END 0x007F0000 / Bank 2 Ending Address /
#define BNK1_END 0x00007F00 / Bank 1 Ending Address /
#define BNK0_END 0x0000007F / Bank 0 Ending Address */
/* ECC Control Register Bit Definitions */
#define MULTI_INT_ENB 0x04 /* Enable Multi-Bit Interrupt /
#define SGL_INT_ENB 0x02 / Enable Single-Bit Interrupt /
#define ECC_ENB 0x01 / ECC Enable for All Four Banks */
/* ECC Status Register Bit Definitions */
#define MBIT_ERR 0x02 /* Multi_Bit Error Detected /
#define SBIT_ERR 0x01 / Single-Bit ECC Error */
/* ECC Check Bit Position Register Masks */
#define ECC_CHK_POS 0x3F /* ECC Data Bit Position */
/* ECC Check Code Test Register Bit Definitions */
#define BAD_CHK_ENB 0x80 /* Enable Bad ECC Check Bits */
/* ECC Check Code Test Register Masks */
#define FRC_BAD_CHK 0x3F /* Force Bad ECC Check Bits */
/* ECC Single-Bit Error Address Register Masks */
#define SB_ADDR 0x0FFFFFFC /* ECC Single-Bit Error Address */
/* ECC Multi-Bit Error Address Register Masks */
#define MB_ADDR 0x0FFFFFFC /* ECC Multi-Bit Error Address /
/******************************************
- WRITE BUFFER AND READ BUFFER REGISTERS *
*******************************************/
#define OFFS_DBCTL 0x0040 /* SDRAM Buffer Control Register */
#define DBCTL (MMCR + OFFS_DBCTL) /* SDRAM Buffer Control Register */
/*
Write Buffer and Read Buffer Bit Definitions
*/
/* SDRAM Buffer Control Register Bit Defitions */
#define RAB_ENB 0x0010 /* Read Ahead Feature Enable */
#define WB_WM_28 0x0000 /* Write Buffer Watermark 28 doublewords /
#define WB_WM_24 0x0040 / Write Buffer Watermark 24 doublewords /
#define WB_WM_16 0x0080 / Write Buffer Watermark 16 doublewords /
#define WB_WM_8 0x00c0 / Write Buffer Watermark 8 doublewords */
#define WB_FLUSH 0x0002 /* Write Buffer Flush /
#define WB_ENB 0x0001 / Write Buffer Enable */
/******************************
- ROM CONTROLLER REGISTERS *
******************************/
#define OFFS_BOOTCSCTL 0x0050 /* /BOOTCS Control Register /
#define OFFS_ROMCS1CTL 0x0054 / /ROMCS1 Control Register /
#define OFFS_ROMCS2CTL 0x0056 / /ROMCS2 Control Register */
#define BOOTCSCTL (MMCR + OFFS_BOOTCSCTL) /* /BOOTCS Control Register /
#define ROMCS1CTL (MMCR + OFFS_ROMCS1CTL) / /ROMCS1 Control Register /
#define ROMCS2CTL (MMCR + OFFS_ROMCS2CTL) / /ROMCS2 Control Register */
/*
ROM Controller Bit Definitions
*/
/* BOOTCS Control Register Bit Definitions */
#define BOOT_DGP 0x1000 /* BOOT CS Device DRAM/GP Select /
#define BOOT_WIDTH_8 0x0000 / BOOT CS Device Width Select 8 bit ROM /
#define BOOT_WIDTH_16 0x0400 / BOOT CS Device Width Select 16 bit ROM /
#define BOOT_WIDTH_32 0x0800 / BOOT CS Device Width Select 32 bit ROM /
//#define BOOT_WIDTH_32 0x0C00 / BOOT CS Device Width Select 32 bit
ROM /
#define BOOT_MODE 0x0200 / BOOT CS Device Mode /
#define BOOT_SUB_DLY_0 0x0000 / Boot CS Device Delay for Subsequent
Access 0 wait states*/
#define BOOT_SUB_DLY_1 0x0010 /* Boot CS Device Delay for Subsequent
Access 1 wait state*/
#define BOOT_SUB_DLY_2 0x0020 /* Boot CS Device Delay for Subsequent
Access 2 wait states*/
#define BOOT_SUB_DLY_3 0x0030 /* Boot CS Device Delay for Subsequent
Access 3 wait states*/
#define BOOT_FIRST_DLY_0 0x0000 /* BOOT CS Device Delay for First
Access 0 wait states /
#define BOOT_FIRST_DLY_1 0x0001 / BOOT CS Device Delay for First
Access 1 wait states /
#define BOOT_FIRST_DLY_2 0x0002 / BOOT CS Device Delay for First
Access 2 wait states /
#define BOOT_FIRST_DLY_3 0x0003 / BOOT CS Device Delay for First
Access 3 wait states /
#define BOOT_FIRST_DLY_4 0x0004 / BOOT CS Device Delay for First
Access 4 wait states /
#define BOOT_FIRST_DLY_5 0x0005 / BOOT CS Device Delay for First
Access 5 wait states /
#define BOOT_FIRST_DLY_6 0x0006 / BOOT CS Device Delay for First
Access 6 wait states /
#define BOOT_FIRST_DLY_7 0x0007 / BOOT CS Device Delay for First
Access 7 wait states */
/* /ROMCS1 & 2 Control Register Bit Definitions */
#define ROM_DGP 0x1000 /* ROM CS Device DRAM/GP Select /
#define ROM_WIDTH_8 0x0000 / ROM CS Device Width Select 8 bit ROM /
#define ROM_WIDTH_16 0x0400 / ROM CS Device Width Select 16 bit ROM /
#define ROM_WIDTH_32 0x0800 / ROM CS Device Width Select 32 bit ROM /
#define ROM_MODE 0x0200 / ROM CS Device Mode /
#define ROM_SUB_DLY_0 0x0000 / ROM CS Device Delay for Subsequent
Access 0 wait states*/
#define ROM_SUB_DLY_1 0x0010 /* ROM CS Device Delay for Subsequent
Access 1 wait state*/
#define ROM_SUB_DLY_2 0x0020 /* ROM CS Device Delay for Subsequent
Access 2 wait states*/
#define ROM_SUB_DLY_3 0x0030 /* ROM CS Device Delay for Subsequent
Access 3 wait states*/
#define ROM_FIRST_DLY_0 0x0000 /* ROM CS Device Delay for First
Access 0 wait states /
#define ROM_FIRST_DLY_1 0x0001 / ROM CS Device Delay for First
Access 1 wait states /
#define ROM_FIRST_DLY_2 0x0002 / ROM CS Device Delay for First
Access 2 wait states /
#define ROM_FIRST_DLY_3 0x0003 / ROM CS Device Delay for First
Access 3 wait states /
#define ROM_FIRST_DLY_4 0x0004 / ROM CS Device Delay for First
Access 4 wait states /
#define ROM_FIRST_DLY_5 0x0005 / ROM CS Device Delay for First
Access 5 wait states /
#define ROM_FIRST_DLY_6 0x0006 / ROM CS Device Delay for First
Access 6 wait states /
#define ROM_FIRST_DLY_7 0x0007 / ROM CS Device Delay for First
Access 7 wait states /
/*****************************
- PCI HOST BRIDGE REGISTERS *
******************************/
/* PCI Memory Mapped Registers */
#define OFFS_HBCTL 0x0060 /* Host Bridge Control Register /
#define OFFS_HBTGTIRQCTL 0x0062 / Host Bridge Target Interrupt
Control Register /
#define OFFS_HBTGTIRQSTA 0x0064 / Host Bridge Target Interrupt
Status Register /
#define OFFS_HBMSTIRQCTL 0x0066 / Host Bridge Target Interrupt
Control Register /
#define OFFS_HBMSTIRQSTA 0x0068 / Host Bridge Master Interrupt
Status Register /
#define OFFS_MSTINTADD 0x006C / Host Bridge Master Interrupt Address
Register */
#define HBCTL (MMCR + OFFS_HBSTL) /* Host Bridge Control Register /
#define HBTGTIRQCTL (MMCR + OFFS_HBTGTIRQCTL) / Host Bridge Target
Interrupt Control Register /
#define HBTGTIRQSTA (MMCR + OFFS_HBTGTIRQSTA) / Host Bridge Target
Interrupt Status Register /
#define HBMSTIRQCTL (MMCR + OFFS_HBMSTIRQCTL) / Host Bridge Target
Interrupt Control Register /
#define HBMSTIRQSTA (MMCR + OFFS_HBMSTIRQSTA) / Host Bridge Master
Interrupt Status Register /
#define MSTINTADD (MMCR + OFFS_MSTINTADD) / Host Bridge Master
Interrupt Address Register */
/* PCI HOST Bridge Direct-Mapped Registers */
#define PCICFGADR 0x0CF8 /* PCI Configuration Address Register /
#define PCICFGDATA 0x0CFC / PCI Configuration Data Register */
/* PCI Configuration Register INDEXES - I/O Address 0Cf8/0CFC */
#define PCIDEVID 0x00 /* Device/Vendor ID Register /
#define PCISTACMD 0x04 / Status Command Register /
#define PCICCREVID 0x08 / Clas Code/Revision ID Register /
#define PCIHEADTYPE 0x0E / Header Type Register /
#define PCIMRETRYTO 0x41 / Master Retry Time-Out Register */
/*
PCI Configuration Bit Definitions
*/
/* Host Bridge Control Register Bit Definitions */
#define PCI_RST 0x8000 /* PCI Reset /
#define T_PURGE_RD_ENB 0x0400 / Target FIFO Purge Enable /
#define T_DLYTR_END_N_RT 0x0000 / Automatic Delayed Transaction
Enable not retried /
#define T_DLYTR_END_RT 0x0100 / Automatic Delayed Transaction Enable
retried /
#define M_WPOST_ENB 0x0008 / Master Controller Write Posting Enable */
/* Host Bridge Target Interrupt Control Register Bit Definitions */
#define T_DLYTO_IRQ_SEL 0x0400 /* Target Delayed Transaction Time-out
Interrupt Select /
#define T_APER_IRQ_SEL 0x0200 / Target Address Parity Interrupt
Select /
#define T_DPER_IRQ_SEL 0x0100 / Target Data Parity Interrupt Select /
#define T_DLYTO_IRQ_ENB 0x0004 / Target Delayed Transaction Time-out
Interrupt Enable /
#define T_APER_IRQ_ENB 0x0002 / Target Address Parity Enable
Interrupt /
#define T_DPER_IRQ_ENB 0x0001 / Target Data Parity Interrupt Enable */
/* Host Bridge Target Interrupt Status Register Bit Definitions */
#define T_IRQ_ID_0 0x0000 /* Target Interrupt Identification PCI 0
active during error /
#define T_IRQ_ID_1 0x0100 / Target Interrupt Identification PCI 1
active during error /
#define T_IRQ_ID_2 0x0200 / Target Interrupt Identification PCI 2
active during error /
#define T_IRQ_ID_3 0x0300 / Target Interrupt Identification PCI 3
active during error /
#define T_IRQ_ID_4 0x0400 / Target Interrupt Identification PCI 4
active during error /
#define T_IRQ_ID_NE 0x0F00 / Target Interrupt Identification No
Error Detected or Bus Value not Latched */
#define T_DLYTO_IQR_STA 0x0004 /* Target Delayed Transaction Time-out
Interrupt Status /
#define T_APER_IRQ_STA 0x0002 / Target Address Parity Interrupt
Status /
#define T_DPER_IRQ_STA 0x0001 / Target Data Parity Interrupt Status */
/* Host Bridge Master Interrupt Control Register Bit Definitions */
#define M_RTRTO_IRQ_SEL 0x2000 /* Master Retry Time-out Interrupt
Select /
#define M_TABRT_IRQ_SEL 0x1000 / Master Target Abort Interrupt Select /
#define M_MARBRT_IRQ_SEL 0x0800 / Master Abort Interrupt Select /
#define M_SERR_IRQ_SEL 0x0400 / Master System Error Interrupt Select /
#define M_RPER_IRQ_SEL 0x0200 / Master Received Parity Error
Interrupt Select /
#define M_DPER_IRQ_SEL 0x0100 / Master Detected Parity Error
interrupt Select /
#define M_RTRTO_IRQ_ENB 0x0020 / Master Retry Time-out Interrupt
Enable /
#define M_TABRT_IRQ_ENB 0x0010 / Master Target Abort Interrupt Enable /
#define M_MARBT_IRQ_ENB 0x0008 / Master Abort Interrupt Enable /
#define M_SERR_IRQ_ENB 0x0004 / Master System Error Interrupt Enable /
#define M_RPER_IRQ_ENB 0x0002 / Master Received Parity Error
Interrupt Enable /
#define M_DPER_IRQ_ENB 0x0001 / Master Detected Parity Error
Interrupt Enable */
#define M_CMD_IRQ_ID_NL 0x0000 /* Master Command Interrupt
Identification - command not latched /
#define M_CMD_IRQ_ID_SC 0x0100 / Master Command Interrupt
Identification - Special Cycle /
#define M_CMD_IRQ_ID_IOR 0x0200 / Master Command Interrupt
Identification - I/O Read /
#define M_CMD_IRQ_ID_IOW 0x0300 / Master Command Interrupt
Identification - I/O Write /
#define M_CMD_IRQ_ID_MR 0x0600 / Master Command Interrupt
Identification - Memory Read /
#define M_CMD_IRQ_ID_MW 0x0700 / Master Command Interrupt
Identification - Memory Write /
#define M_CMD_IRQ_ID_CR 0x0A00 / Master Command Interrupt
Identification - Configuration Read /
#define M_CMD_IRQ_ID_CW 0x0B00 / Master Command Interrupt
Identification - Configuration Write /
#define M_CMD_IRQ_ID_MRM 0x0C00 / Master Command Interrupt
Identification - Memory Read Multiple /
#define M_CMD_IRQ_ID_DAC 0x0D00 / Master Command Interrupt
Identification - Dual Access Cycle (not used by Elan SC520) /
#define M_CMD_IRQ_ID_MRL 0x0E00 / Master Command Interrupt
Identification - Memory Read Line /
#define M_CMD_IRQ_ID_MWI 0x0F00 / Master Command Interrupt
Identification - Memory Write and Invalidate */
#define M_RTRTO_IRQ_STA 0x0020 /* Master Retry Time-out Interrupt
Status /
#define M_TABRT_IRQ_STA 0x0010 / Master Target Abort Interrupt Status /
#define M_MABRT_IRQ_STA 0x0008 / Master Abort Interrupt Status /
#define M_SERR_IRQ_STA 0x0004 / Master System Error Interrupt Status /
#define M_RPER_IRQ_STA 0x0002 / Master Received Parity Error
Interrupt Status /
#define M_DPER_IRQ_STA 0x0001 / Master Detected Parity Error
Interrupt Status */
/* PCI Configuration Address Register Bit Definitions */
#define PCI_CFG_ENABLE 0x8000 /* PCI Config Enable Bit */
/* PCI Configuration Address Register Masks */
#define BUS_NUM 0x00FF0000 /* Bus Number /
#define DEVICE_NUM 0x0000F800 / Device Number /
#define FUNCTION_NUM 0x00000700 / Function Number /
#define REGISTER_NUM 0x000000FC / Register Number */
/* PCI Configuration Data Register Masks */
#define CFG_DATA 0xFFFFFFFF /* Configuration Data */
/* Device/Vendor ID Register Masks */
#define DEV_ID 0xFFFF0000 /* Device ID /
#define VDR_ID 0x0000FFFF / Vendor ID */
/* Status/Command Register Bit Definitions */
#define PERR_DET 0x80000000 /* Parity Error Detect /
#define SIG_SERR 0x40000000 / Signalled System Error /
#define R_MST_ABT 0x20000000 / Received Master Abort /
#define R_TGT_ABT 0x10000000 / Received Target Abort /
#define S_TGT_ABT 0x08000000 / Signalled Target Abort /
#define S_DVSL_TIM 0x02000000 / Device Select Timing field always 01 /
#define D_PERR_DET 0x01000000 / Data Parity Reported /
#define FBTB 0x00800000 / Fast Back to Back Capable /
#define UDFS 0x00400000 / UDF Supported /
#define M_CAP_66 0x00200000 / 66 Mhz Capable /
#define SERR_ENB 0x00000100 / /SERR Enable /
#define PERR_RES 0x00000040 / Parity Error Response /
#define BUS_MAS 0x00000004 / Master Enable /
#define MEM_ENB 0x00000002 / Memory Access Enable /
#define IO_ENB 0x00000001 / I/O Space Enable */
/* Class Code/Revision ID Register Masks */
#define CL_CD 0xFF000000 /* Base Class Code /
#define SBCL_CD 0x00FF0000 / Sub Class Code /
#define PRG_IF 0x0000FF00 / Program Interface /
#define REV_ID 0x000000FF / Revision I.D. */
/* Header Type Register Masks */
#define HDR_TYP 0xFF /* Header Type */
/* Master REtry Time-out Register Masks */
#define M_RETRY_TO 0xFF /* Master Retry Time-out */
/**********************************
- System Arbiter Registers *
**********************************/
#define OFFS_SYSARBCTL 0x0070 /* System Arbiter Control Register /
#define OFFS_PCIARBSTA 0x0071 / PCI Bus Arbiter Status Register /
#define OFFS_SYSARBMENB 0x0072 / System Arbiter Master Enable Register /
#define OFFS_ARBPRICTL 0x0074 / Arbiter Priority Control Register */
#define SYSARBCTL (MMCR + OFFS_SYSARBCTL) /* System Arbiter Control
Register /
#define PCIARBSTA (MMCR + OFFS_PCIARBSTA) / PCI Bus Arbiter Status
Register /
#define SYSARBMENB (MMCR + OFFS_SYSARBMENB)/ System Arbiter Master
Enable Register /
#define ARBPRICTL (MMCR + OFFS_ARBPRICTL) / Arbiter Priority Control
Register */
/*
System Arbiter Register Bit Definitions
*/
/* System Arbiter Control Register Bit Definitions */
#define BUS_PARK_SEL 0x04 /* PCI BUS Arbiter Bus Park /
#define CNCR_MODE_ENB 0x02 / System Arbiter Concurrent Mode Enable /
#define GNT_TO_INT_ENB 0x01 / PCI Bus Arbiter Grant Time-out
Interrupt Enable */
/* PCI Bus Arbiter Status Register Bit Definitions */
#define GNT_TO_STA 0x80 /* PCI Cus Arbiter Grant Time-out Status */
#define GNT_TO_ID_0 0x00 /* PCI Arbiter Grant Time-out
Identification: /GNT0 asserted during grant time-out /
#define GNT_TO_ID_1 0x01 / PCI Arbiter Grant Time-out
Identification: /GNT1 asserted during grant time-out /
#define GNT_TO_ID_2 0x02 / PCI Arbiter Grant Time-out
Identification: /GNT2 asserted during grant time-out /
#define GNT_TO_ID_3 0x03 / PCI Arbiter Grant Time-out
Identification: /GNT3 asserted during grant time-out /
#define GNT_TO_ID_4 0x04 / PCI Arbiter Grant Time-out
Identification: /GNT4 asserted during grant time-out /
#define GNT_TO_ID_Am5x86 0x0E / PCI Arbiter Grant Time-out
Identification: Am5x86 /GNT asserted during grant time-out /
#define GNT_TO_ID_NGT 0x0F / PCI Arbiter Grant Time-out
Identification: No Grant Timeout detected or /GNT asserted
when grant time-out asserted but not latched */
/* System Arbiter Master Enable Register Bit Definitions */
#define REQ4_ENB 0x0010 /* PCI Bus Arbiter Request #4 Enable /
#define REQ3_ENB 0x0008 / PCI Bus Arbiter Request #3 Enable /
#define REQ2_ENB 0x0004 / PCI Bus Arbiter Request #2 Enable /
#define REQ1_ENB 0x0002 / PCI Bus Arbiter Request #1 Enable /
#define REQ0_ENB 0x0001 / PCI Bus Arbiter Request #0 Enable */
/* Arbiter Control Register Bit Definitions */
#define CPU_PRI_1 0x40000000 /* PCI Bus Arbiter CPU Priority: CPU
granted PCI Bus every 1 PCI Master Cycle /
#define CPU_PRI_2 0x80000000 / PCI Bus Arbiter CPU Priority: CPU
granted PCI Bus every 2 PCI Master Cycles /
#define CPU_PRI_3 0xc0000000 / PCI Bus Arbiter CPU Priority: CPU
granted PCI Bus every 3 PCI Master Cycles */
/* position 1 of high priority queue /
#define HI_PRI_1_SEL_R0G0 0x00000000 / PCI Bus Arbiter High Priority
1: PCI Bus Master connected to /REQ0 and /GNT0 in queue /
#define HI_PRI_1_SEL_R1G1 0x00000100 / PCI Bus Arbiter High Priority
1: PCI Bus Master connected to /REQ1 and /GNT1 in queue /
#define HI_PRI_1_SEL_R2G2 0x00000200 / PCI Bus Arbiter High Priority
1: PCI Bus Master connected to /REQ2 and /GNT2 in queue /
#define HI_PRI_1_SEL_R3G3 0x00000300 / PCI Bus Arbiter High Priority
1: PCI Bus Master connected to /REQ3 and /GNT3 in queue /
#define HI_PRI_1_SEL_R4G4 0x00000400 / PCI Bus Arbiter High Priority
1: PCI Bus Master connected to /REQ4 and /GNT4 in queue /
#define HI_PRI_1_SEL_NM 0x00000F00 / PCI Bus Arbiter High Priority 1:
No Master is in position 1 of queue */
/* position 0 of high priority queue /
#define HI_PRI_0_SEL_R0G0 0x00000000 / PCI Bus Arbiter High Priority
0: PCI Bus Master connected to /REQ0 and /GNT0 in queue /
#define HI_PRI_0_SEL_R1G1 0x00000001 / PCI Bus Arbiter High Priority
0: PCI Bus Master connected to /REQ1 and /GNT1 in queue /
#define HI_PRI_0_SEL_R2G2 0x00000002 / PCI Bus Arbiter High Priority
0: PCI Bus Master connected to /REQ2 and /GNT2 in queue /
#define HI_PRI_0_SEL_R3G3 0x00000003 / PCI Bus Arbiter High Priority
0: PCI Bus Master connected to /REQ3 and /GNT3 in queue /
#define HI_PRI_0_SEL_R4G4 0x00000004 / PCI Bus Arbiter High Priority
0: PCI Bus Master connected to /REQ4 and /GNT4 in queue /
#define HI_PRI_0_SEL_NM 0x0000000F / PCI Bus Arbiter High Priority 0:
No Master is in position 0 of queue /
/*********************************
- Memory and I/O Space Registers *
**********************************/
#define OFFS_ADDDECCTL 0x0080 /* Address Decode Control Register /
#define OFFS_WPVSTA 0x0082 / Write-Protect Violation Status
Register /
#define OFFS_PAR0 0x0088 / Programmable Address Region 0
Register /
#define OFFS_PAR1 0x008c / Programmable Address Region
1 Register /
#define OFFS_PAR2 0x0090 / Programmable Address Region
2 Register /
#define OFFS_PAR3 0x0094 / Programmable Address Region
3 Register /
#define OFFS_PAR4 0x0098 / Programmable Address Region
4 Register /
#define OFFS_PAR5 0x009c / Programmable Address Region
5 Register /
#define OFFS_PAR6 0x00a0 / Programmable Address Region 6
Register /
#define OFFS_PAR7 0x00a4 / Programmable Address Region
7 Register /
#define OFFS_PAR8 0x00a8 / Programmable Address Region
8 Register /
#define OFFS_PAR9 0x00ac / Programmable Address Region
9 Register /
#define OFFS_PAR10 0x00b0 / Programmable Address Region
10 Register /
#define OFFS_PAR11 0x00b4 / Programmable Address Region
11 Register /
#define OFFS_PAR12 0x00b8 / Programmable Address Region
12 Register /
#define OFFS_PAR13 0x00bc / Programmable Address Region
13 Register /
#define OFFS_PAR14 0x00c0 / Programmable Address Region
14 Register /
#define OFFS_PAR15 0x00c4 / Programmable Address Region 15 Register */
#define ADDDECCTL (MMCR + OFFS_ADDDECCTL) /* Address Decode Control
Register /
#define WPVSTA (MMCR + OFFS_WPVSTA) / Write-Protect Violation
Status Register /
#define PAR0 (MMCR + OFFS_PAR0) / Programmable Address
Region 0 Register /
#define PAR1 (MMCR + OFFS_PAR1) / Programmable Address
Region 1 Register /
#define PAR2 (MMCR + OFFS_PAR2) / Programmable Address
Region 2 Register /
#define PAR3 (MMCR + OFFS_PAR3) / Programmable Address
Region 3 Register /
#define PAR4 (MMCR + OFFS_PAR4) / Programmable Address
Region 4 Register /
#define PAR5 (MMCR + OFFS_PAR5) / Programmable Address
Region 5 Register /
#define PAR6 (MMCR + OFFS_PAR6) / Programmable Address
Region 6 Register /
#define PAR7 (MMCR + OFFS_PAR7) / Programmable Address
Region 7 Register /
#define PAR8 (MMCR + OFFS_PAR8) / Programmable Address
Region 8 Register /
#define PAR9 (MMCR + OFFS_PAR9) / Programmable Address
Region 9 Register /
#define PAR10 (MMCR + OFFS_PAR10) / Programmable Address
Region 10 Register /
#define PAR11 (MMCR + OFFS_PAR11) / Programmable Address
Region 11 Register /
#define PAR12 (MMCR + OFFS_PAR12) / Programmable Address
Region 12 Register /
#define PAR13 (MMCR + OFFS_PAR13) / Programmable Address
Region 13 Register /
#define PAR14 (MMCR + OFFS_PAR14) / Programmable Address
Region 14 Register /
#define PAR15 (MMCR + OFFS_PAR15) / Programmable Address Region 15
Register */
#define CBAR 0XFFFC /* Configuration Base Address Register */
/*
Memory and I/O Space Register Bit Definitions
*/
/* Address Decode Control Register Bit Definitions */
#define WPV_INT_ENB 0x80 /* Write-Protect Violation Interrupt Enable /
#define IO_HOLE_DEST 0x10 / I/O Holde Access Destination /
#define RTC_DIS 0x04 / RTC Disable /
#define UART2_DIS 0x02 / UART2 Disable /
#define UART1_DIS 0x01 / UART1 Disable */
/* Write_Protect Violation Status Register Bit Definitions */
#define WPC_STA 0x8000 /* Write-Protect Violation Interrupt Status /
#define WPV_MSTR_CPU 0x0000 / Write-Protect Violation Master: CPU /
#define WPV_MSTR_PCI 0x0100 / Write-Protect Violation Master: PCI
bus Master /
#define WPV_MSTR_GPDMA 0x0200 / Write-Protect Violation Master: GP
DMA */
/* Write_Protect Violation Status Register Masks /
#define WPV_WINDOW 0x000F / Write_Protection Window Number */
/* PAR Register Bit Definitions */
#define TARGET_DIS 0x00000000 /* Target of the PARx Window: window
disabled /
#define TARGET_GP_IO 0x20000000 / Target of the PARx Window: GP Bus
I/O Region /
#define TARGET_GP_MEM 0x40000000 / Target of the PARx Window: GP Bus
Memory Region /
#define TARGET_PCI_MEM 0x60000000 / Target of the PARx Window: PCI
Memory Region /
#define TARGET_BOOTCS 0x80000000 / Target of the PARx Window: /BOOTCS
Region /
#define TARGET_ROMCS1 0xA0000000 / Target of the PARx Window: /ROMCS1
Region /
#define TARGET_ROMCS2 0xC0000000 / Target of the PARx Window: /ROMCS2
Region /
#define TARGET_SDRAM 0xE0000000 / Target of the PARx Window: SDRAM
region */
#define ATTR_GPCS0 0x00000000 /* Attribute Bit Field: GP Bus Chip
Select 0 /
#define ATTR_GPCS1 0x04000000 / Attribute Bit Field: GP Bus Chip
Select 1 /
#define ATTR_GPCS2 0x08000000 / Attribute Bit Field: GP Bus Chip
Select 2 /
#define ATTR_GPCS3 0x0C000000 / Attribute Bit Field: GP Bus Chip
Select 3 /
#define ATTR_GPCS4 0x10000000 / Attribute Bit Field: GP Bus Chip
Select 4 /
#define ATTR_GPCS5 0x14000000 / Attribute Bit Field: GP Bus Chip
Select 5 /
#define ATTR_GPCS6 0x18000000 / Attribute Bit Field: GP Bus Chip
Select 6 /
#define ATTR_GPCS7 0x1C000000 / Attribute Bit Field: GP Bus Chip
Select 7 /
#define PG_SZ 0x02000000 / Page Size */
/* PAR Register Masks */
#define TARGET 0xE0000000 /* Target of PARx Window /
#define ATTR 0x1C000000 / Attribute Field /
#define SZ_ST_ADR 0x00FFFFFF / Region Size/Start Address */
/* Configuration Base Address Register Bit Definitions */
#define ENABLE 0x80000000 /* Enable Bit */
/* Configuration Base Address Register Masks */
#define ADR 0x3FFFF000 /* Start Address /
#define MATCH 0x000000FF / Match */
/************************************************
- General Purpose (GP) Bus Controller Registers *
************************************************/
#define OFFS_GPECHO 0x0c00 /* GP Echo Mode Register /
#define OFFS_GPCSDW 0x0c01 / GP Chip Select Data Width Register /
#define OFFS_GPCSQUAL 0x0c02 / GP Chip Select Qualification Register /
#define OFFS_GPCSRT 0x0c08 / GP Chip Select Recovery Time Register /
#define OFFS_GPCSPW 0x0c09 / GP Chip Select Pulse Width Register /
#define OFFS_GPCSOFF 0x0c0a / GP Chip Select Offset Register /
#define OFFS_GPRDW 0x0c0b / GP Read Pulse Width Register /
#define OFFS_GPRDOFF 0x0c0c / GP Read Offset Register /
#define OFFS_GPWRW 0x0c0d / GP Write Pulse Width Register /
#define OFFS_GPWROFF 0x0c0e / GP Write Offset Register /
#define OFFS_GPALEW 0x0c0f / GP ALE Pulse Width Register /
#define OFFS_GPALEOFF 0x0c10 / GP ALE Offset Register */
#define GPECHO (MMCR + OFFS_GPECHO) /* GP Echo Mode Register /
#define GPCSDW (MMCR + OFFS_GPCSDW) / GP Chip Select Data Width
Register /
#define GPCSQUAL (MMCR + OFFS_GPCSQUAL) / GP Chip Select Qualification
Register /
#define GPCSRT (MMCR + OFFS_GPCSRT) / GP Chip Select Recovery Time
Register /
#define GPCSPW (MMCR + OFFS_GPCSPW) / GP Chip Select Pulse Width
Register /
#define GPCSOFF (MMCR + OFFS_GPCSOFF) / GP Chip Select Offset
Register /
#define GPRDW (MMCR + OFFS_GPRDW) / GP Read Pulse Width Register /
#define GPRDOFF (MMCR + OFFS_GPRDOFF) / GP Read Offset Register /
#define GPWRW (MMCR + OFFS_GPWRW) / GP Write Pulse Width Register /
#define GPWROFF (MMCR + OFFS_GPWROFF) / GP Write Offset Register /
#define GPALEW (MMCR + OFFS_GPALEW) / GP ALE Pulse Width Register /
#define GPALEOFF (MMCR + OFFS_GPALEOFF) / GP ALE Offset Register */
/*
General Purpose (DP) Bus Controller Register Bit Definitions
*/
/* GP Echo Mode Register Bit Definitions */
#define GP_ECHO_ENB 0x01 /* GP Bus Echo Mode Enable */
/* GP Chip Select Data Width Register Bit Definitions */
#define GPCS7_DW 0x80 /* Data Width Select for /GPCS7 /
#define GPCS6_DW 0x40 / Data Width Select for /GPCS6 /
#define GPCS5_DW 0x20 / Data Width Select for /GPCS5 /
#define GPCS4_DW 0x10 / Data Width Select for /GPCS4 /
#define GPCS3_DW 0x08 / Data Width Select for /GPCS3 /
#define GPCS2_DW 0x04 / Data Width Select for /GPCS2 /
#define GPCS1_DW 0x02 / Data Width Select for /GPCS1 /
#define GPCS0_DW 0x01 / Data Width Select for /GPCS0 */
/* GP Chip Select Qualification Register Bit Definitions */
#define GPCS7_RW_NQ 0x0000 /* /GPCS7 Qualifier Selection: No
qualification /
#define GPCS7_RW_QCSWWS 0x4000 / /GPCS7 Qualifier Selection: Qualifiy
chip select with write strobes (/GPIOWR or /GPMEMWR) /
#define GPCS7_RW_QCSWRS 0x8000 / /GPCS7 Qualifier Selection: Qualifiy
chip select with read strobes (/GPIORD or /GPMEMRD) /
#define GPCS7_RW_QCSWBS 0xC000 / /GPCS7 Qualifier Selection: Qualifiy
chip select with both strobes */
#define GPCS6_RW_NQ 0x0000 /* /GPCS6 Qualifier Selection: No
qualification /
#define GPCS6_RW_QCSWWS 0x1000 / /GPCS6 Qualifier Selection: Qualifiy
chip select with write strobes (/GPIOWR or /GPMEMWR) /
#define GPCS6_RW_QCSWRS 0x2000 / /GPCS6 Qualifier Selection: Qualifiy
chip select with read strobes (/GPIORD or /GPMEMRD) /
#define GPCS6_RW_QCSWBS 0x3000 / /GPCS6 Qualifier Selection: Qualifiy
chip select with both strobes */
#define GPCS5_RW_NQ 0x0000 /* /GPCS5 Qualifier Selection: No
qualification /
#define GPCS5_RW_QCSWWS 0x0400 / /GPCS5 Qualifier Selection: Qualifiy
chip select with write strobes (/GPIOWR or /GPMEMWR) /
#define GPCS5_RW_QCSWRS 0x0800 / /GPCS5 Qualifier Selection: Qualifiy
chip select with read strobes (/GPIORD or /GPMEMRD) /
#define GPCS5_RW_QCSWBS 0x0C00 / /GPCS5 Qualifier Selection: Qualifiy
chip select with both strobes */
#define GPCS4_RW_NQ 0x0000 /* /GPCS4 Qualifier Selection: No
qualification /
#define GPCS4_RW_QCSWWS 0x0100 / /GPCS4 Qualifier Selection: Qualifiy
chip select with write strobes (/GPIOWR or /GPMEMWR) /
#define GPCS4_RW_QCSWRS 0x0200 / /GPCS4 Qualifier Selection: Qualifiy
chip select with read strobes (/GPIORD or /GPMEMRD) /
#define GPCS4_RW_QCSWBS 0x0300 / /GPCS4 Qualifier Selection: Qualifiy
chip select with both strobes */
#define GPCS3_RW_NQ 0x0000 /* /GPCS3 Qualifier Selection: No
qualification /
#define GPCS3_RW_QCSWWS 0x0040 / /GPCS3 Qualifier Selection: Qualifiy
chip select with write strobes (/GPIOWR or /GPMEMWR) /
#define GPCS3_RW_QCSWRS 0x0080 / /GPCS3 Qualifier Selection: Qualifiy
chip select with read strobes (/GPIORD or /GPMEMRD) /
#define GPCS3_RW_QCSWBS 0x00C0 / /GPCS3 Qualifier Selection: Qualifiy
chip select with both strobes */
#define GPCS2_RW_NQ 0x0000 /* /GPCS2 Qualifier Selection: No
qualification /
#define GPCS2_RW_QCSWWS 0x0010 / /GPCS2 Qualifier Selection: Qualifiy
chip select with write strobes (/GPIOWR or /GPMEMWR) /
#define GPCS2_RW_QCSWRS 0x0020 / /GPCS2 Qualifier Selection: Qualifiy
chip select with read strobes (/GPIORD or /GPMEMRD) /
#define GPCS2_RW_QCSWBS 0x0030 / /GPCS2 Qualifier Selection: Qualifiy
chip select with both strobes */
#define GPCS1_RW_NQ 0x0000 /* /GPCS1 Qualifier Selection: No
qualification /
#define GPCS1_RW_QCSWWS 0x0004 / /GPCS1 Qualifier Selection: Qualifiy
chip select with write strobes (/GPIOWR or /GPMEMWR) /
#define GPCS1_RW_QCSWRS 0x0008 / /GPCS1 Qualifier Selection: Qualifiy
chip select with read strobes (/GPIORD or /GPMEMRD) /
#define GPCS1_RW_QCSWBS 0x000C / /GPCS1 Qualifier Selection: Qualifiy
chip select with both strobes */
#define GPCS0_RW_NQ 0x0000 /* /GPCS0 Qualifier Selection: No
qualification /
#define GPCS0_RW_QCSWWS 0x0001 / /GPCS0 Qualifier Selection: Qualifiy
chip select with write strobes (/GPIOWR or /GPMEMWR) /
#define GPCS0_RW_QCSWRS 0x0002 / /GPCS0 Qualifier Selection: Qualifiy
chip select with read strobes (/GPIORD or /GPMEMRD) /
#define GPCS0_RW_QCSWBS 0x0003 / /GPCS0 Qualifier Selection: Qualifiy
chip select with both strobes */
/* GP Chip Select Recovery Time Register Masks */
#define GPCS_RECOVR 0xFF /* Chip Select Recovery Time */
/* GP Chip Select Pulse Width Register Masks */
#define GPCS_WIDTH 0xFF /* Signal Width for the GP Bus Chip Selects */
/* GP Chip Select Offset Register Masks */
#define GPCS_OFF 0xFF /* Offset Time for the GP Bus Chip Select */
/* GP Read Pulse Width Register Masks */
#define GP_RD_WIDTH 0xFF /* Signal Width for /GPIORD and /GPMEMRD */
/* GP Read Offset Register Masks */
#define GP_RD_OFF 0xFF /* Offset Time for /GPIORD and /GPMEMRD */
/* GP Write Pulse Width Register Masks */
#define GP_WR_WIDTH 0xFF /* Signal Width for write strobes /GPIOQR
and /GPMEMWR */
/* GP Write Offset Register Masks */
#define GP_WR_OFF 0xFF /* Offset Time for /GPIOWR and /GPMEMWR */
/* GP ALE Pulse Width Register Masks */
#define GP_ALE_WIDTH 0xFF /* Signal Width for GPALE */
/* GP ALE Offset Register Masks */
#define GPA_LE_OFF 0xFF /* Offset Time for GPALE */
/*******************************************
- Programmable I/O Configuration Registers *
*******************************************/
#define OFFS_PIOPFS15_0 0x0c20 /* PIO15-PIO0 Pin Function Select /
#define OFFS_PIOPFS31_16 0x0c22 / PIO31-PIO16 Pin Function Select /
#define OFFS_CSPFS 0x0c42 / Chip Select Pin Function Select /
#define OFFS_CLKSEL 0x0c26 / Clock Select /
#define OFFS_DSCTL 0x0c28 / Drive Strength Control /
#define OFFS_PIODIR15_0 0x0c2a / PIO15-PIO0 Direction /
#define OFFS_PIODIR31_16 0x0c2c / PIO31-PIO16 Direction /
#define OFFS_PIODATA15_0 0x0c30 / PIO15-PIO0 Data /
#define OFFS_PIODATA31_16 0x0c32 / PIO31-PIO16 Data /
#define OFFS_PIOSET15_0 0x0c34 / PIO15-PIO0 Set /
#define OFFS_PIOSET31_16 0x0c36 / PIO31-PIO16 Set /
#define OFFS_PIOCLR15_0 0x0c38 / PIO15-PIO0 Clear /
#define OFFS_PIOCLR31_16 0x0c3a / PIO31-PIO16 Clear */
#define PIOPFS15_0 (MMCR + OFFS_PIOPFS15_0) /* PIO15-PIO0 Pin Function
Select /
#define PIOPFS31_16 (MMCR + OFFS_PIOPFS31_16) / PIO31-PIO16 Pin
Function Select /
#define CSPFS (MMCR + OFFS_CSPFS) / Chip Select Pin Function Select /
#define CLKSEL (MMCR + OFFS_CLKSEL) / Clock Select /
#define DSCTL (MMCR + OFFS_DSCTL) / Drive Strength Control /
#define PIODIR15_0 (MMCR + OFFS_PIODIR15_0) / PIO15-PIO0 Direction /
#define PIODIR31_16 (MMCR + OFFS_PIODIR31_16) / PIO31-PIO16 Direction /
#define PIODATA15_0 (MMCR + OFFS_PIODATA15_0) / PIO15-PIO0 Data /
#define PIODATA31_16 (MMCR + OFFS_PIODATA31_16) / PIO31-PIO16 Data /
#define PIOSET15_0 (MMCR + OFFS_PIOSET15_0) / PIO15-PIO0 Set /
#define PIOSET31_16 (MMCR + OFFS_PIOSET31_16) / PIO31-PIO16 Set /
#define PIOCLR15_0 (MMCR + OFFS_PIOCLR15_0) / PIO15-PIO0 Clear /
#define PIOCLR31_16 (MMCR + OFFS_PIOCLR31_16) / PIO31-PIO16 Clear */
/*
Programmable I/O Configuration Register Bit Definitions
*/
/* PIO15-PIO0 Pin Function Select Bit Definitions */
#define PIO15_FNC 0x8000 /* PIO15 or GPIRQ8 Function Select /
#define PIO14_FNC 0x4000 / PIO14 or GPIRQ9 Function Select /
#define PIO13_FNC 0x2000 / PIO13 or GPIRQ10 Function Select /
#define PIO12_FNC 0x1000 / PIO12 or /GPDACK0 Function Select /
#define PIO11_FNC 0x0800 / PIO11 or /GPDACK1 Function Select /
#define PIO10_FNC 0x0400 / PIO10 or /GPDACK2 Function Select /
#define PIO9_FNC 0x0200 / PIO9 or /GPDACK3 Function Select /
#define PIO8_FNC 0x0100 / PIO8 or GPDRQ0 Function Select /
#define PIO7_FNC 0x0080 / PIO7 or GPDRQ1 Function Select /
#define PIO6_FNC 0x0040 / PIO6 or GPDRQ2 Function Select /
#define PIO5_FNC 0x0020 / PIO5 or GPDRQ3 Function Select /
#define PIO4_FNC 0x0010 / PIO4 or GPTC Function Select /
#define PIO3_FNC 0x0008 / PIO3 or GPAEN Function Select /
#define PIO2_FNC 0x0004 / PIO2 or GPRDY Function Select /
#define PIO1_FNC 0x0002 / PIO1 or /GPBHE Function Select /
#define PIO0_FNC 0x0001 / PIO0 or /GPALE Function Select */
/* PIO31-PIO16 Pin Function Select Bit Definitions */
#define PIO31_FNC 0x8000 /* PIO31 or /RIN2 Function Select /
#define PIO30_FNC 0x4000 / PIO30 or /DCD2 Function Select /
#define PIO29_FNC 0x2000 / PIO29 or /DSR2 Function Select /
#define PIO28_FNC 0x1000 / PIO28 or /CTS2 Function Select /
#define PIO27_FNC 0x0800 / PIO27 or /GPCS0 Function Select /
#define PIO26_FNC 0x0400 / PIO26 or /GPMEMCS16 Function Select /
#define PIO25_FNC 0x0200 / PIO25 or /GPIOCS16 Function Select /
#define PIO24_FNC 0x0100 / PIO24 or /GPDBUFOE Function Select /
#define PIO23_FNC 0x0080 / PIO23 or GPIRQ0 Function Select /
#define PIO22_FNC 0x0040 / PIO22 or GPIRQ1 Function Select /
#define PIO21_FNC 0x0020 / PIO21 or GPIRQ2 Function Select /
#define PIO20_FNC 0x0010 / PIO20 or GPIRQ3 Function Select /
#define PIO19_FNC 0x0008 / PIO19 or GPIRQ4 Function Select /
#define PIO18_FNC 0x0004 / PIO18 or GPIRQ5 Function Select /
#define PIO17_FNC 0x0002 / PIO17 or GPIRQ6 Function Select /
#define PIO16_FNC 0x0001 / PIO16 or GPIRQ7 Function Select */
/* Chip Select Pin Function Select Register Bit Definitions */
#define GPCS7_SEL 0x80 /* /GPCS7 or TMROUT0 Function Select /
#define GPCS6_SEL 0x40 / /GPCS6 or TMROUT1 Function Select /
#define GPCS5_SEL 0x20 / /GPCS5 or TMRIN0 Function Select /
#define GPCS4_SEL 0x10 / /GPCS4 or TMRIN1 Function Select /
#define GPCS3_SEL 0x08 / /GPCS3 or PITGATE2 Function Select /
#define GPCS2_SEL 0x04 / /ROMCS2 or /GPCS2 Function Select /
#define GPCS1_SEL 0x02 / /ROMCS1 or /GPCS1 Function Select */
/* Clock Select Register Bit Definitions */
#define CLK_TST_SEL_RTC 0x00 /* CLKTEST pin output clock select:
32.768 Khz (RTC clock) /
#define CLK_TST_SEL_UART1 0x10 / CLKTEST pin output clock select:
1.8432 Mhz (UART clock) /
#define CLK_TST_SEL_UART2 0x20 / CLKTEST pin output clock select:
18.432 Mhz (UART clock) /
#define CLK_TST_SEL_PIT 0x30 / CLKTEST pin output clock select:
1.1882 Mhz (PIT clock) /
#define CLK_TST_SEL_PLL1 0x40 / CLKTEST pin output clock select:
1.47456 Mhz (PLL1 clock) /
#define CLK_TST_SEL_PLL2 0x50 / CLKTEST pin output clock select:
36.864 Mhz (PLL2 clock) /
#define CLK_TST_SEL_0V 0x60 / CLKTEST pin output clock select: DC
(0V) */
#define CLK_PIN_DIR 0x02 /* CLKTIMER[CLKTEST] Pin Direction /
#define CLK_PIN_ENB 0x01 / CLKTIMER[CLKTEST] Pin Enable */
/* Drive Strength Control Register Bit Definitions */
#define SCS_DRIVE_12ma 0x0100 /* I/O Pad Drive Strength for
/SCS3-/SCS0: 12-ma Pads /
#define SCS_DRIVE_18ma 0x0200 / I/O Pad Drive Strength for
/SCS3-/SCS0: 18-ma Pads */
#define SRCW_DRIVE_24ma 0x0000 /* I/O Pad Drive Strength for
/SRASB-/SRASA,/SCASB-/SCASA,/SWEB-/SWEA 24-ma Pads /
#define SRCW_DRIVE_12ma 0x0040 / I/O Pad Drive Strength for
/SRASB-/SRASA,/SCASB-/SCASA,/SWEB-/SWEA 12-ma Pads /
#define SRCW_DRIVE_18ma 0x0080 / I/O Pad Drive Strength for
/SRASB-/SRASA,/SCASB-/SCASA,/SWEB-/SWEA 18-ma Pads */
#define SDQM_DRIVE_24 0x0000 /* I/O Pad Drive Strength for
SDQM3-SDQM0: 24-ma pads /
#define SDQM_DRIVE_12 0x0010 / I/O Pad Drive Strength for
SDQM3-SDQM0: 12-ma pads /
#define SDQM_DRIVE_18 0x0020 / I/O Pad Drive Strength for
SDQM3-SDQM0: 18-ma pads */
#define MA_DRIVE_24 0x0000 /* I/O Pad Drive Strength for MA14-MA0:
24-ma pads /
#define MA_DRIVE_12 0x0004 / I/O Pad Drive Strength for MA14-MA0:
12-ma pads /
#define MA_DRIVE_18 0x0008 / I/O Pad Drive Strength for MA14-MA0:
18-ma pads */
#define DATA_DRIVE_24 0x0000 /* I/O Pad Drive Strength for MD31-MD0
and MECC6-MECC0: 24ma pads /
#define DATA_DRIVE_12 0x0001 / I/O Pad Drive Strength for MD31-MD0
and MECC6-MECC0: 12ma pads /
#define DATA_DRIVE_18 0x0002 / I/O Pad Drive Strength for MD31-MD0
and MECC6-MECC0: 18ma pads */
/* PIO15-PIO0 Direction Register Bit Definitions */
#define PIO15_DIR 0x8000 /* PIO15 Output or Input Select /
#define PIO14_DIR 0x4000 / PIO14 Output or Input Select /
#define PIO13_DIR 0x2000 / PIO13 Output or Input Select /
#define PIO12_DIR 0x1000 / PIO12 Output or Input Select /
#define PIO11_DIR 0x0800 / PIO11 Output or Input Select /
#define PIO10_DIR 0x0400 / PIO10 Output or Input Select /
#define PIO9_DIR 0x0200 / PIO9 Output or Input Select /
#define PIO8_DIR 0x0100 / PIO8 Output or Input Select /
#define PIO7_DIR 0x0080 / PIO7 Output or Input Select /
#define PIO6_DIR 0x0040 / PIO6 Output or Input Select /
#define PIO5_DIR 0x0020 / PIO5 Output or Input Select /
#define PIO4_DIR 0x0010 / PIO4 Output or Input Select /
#define PIO3_DIR 0x0008 / PIO3 Output or Input Select /
#define PIO2_DIR 0x0004 / PIO2 Output or Input Select /
#define PIO1_DIR 0x0002 / PIO1 Output or Input Select /
#define PIO0_DIR 0x0001 / PIO0 Output or Input Select */
/* PIO31-PIO16 Direction Register Bit Definitions */
#define PIO31_DIR 0x8000 /* PIO31 Output or Input Select /
#define PIO30_DIR 0x4000 / PIO30 Output or Input Select /
#define PIO29_DIR 0x2000 / PIO29 Output or Input Select /
#define PIO28_DIR 0x1000 / PIO28 Output or Input Select /
#define PIO27_DIR 0x0800 / PIO27 Output or Input Select /
#define PIO26_DIR 0x0400 / PIO26 Output or Input Select /
#define PIO25_DIR 0x0200 / PIO25 Output or Input Select /
#define PIO24_DIR 0x0100 / PIO24 Output or Input Select /
#define PIO23_DIR 0x0080 / PIO23 Output or Input Select /
#define PIO22_DIR 0x0040 / PIO22 Output or Input Select /
#define PIO21_DIR 0x0020 / PIO21 Output or Input Select /
#define PIO20_DIR 0x0010 / PIO20 Output or Input Select /
#define PIO19_DIR 0x0008 / PIO19 Output or Input Select /
#define PIO18_DIR 0x0004 / PIO18 Output or Input Select /
#define PIO17_DIR 0x0002 / PIO17 Output or Input Select /
#define PIO16_DIR 0x0001 / PIO16 Output or Input Select */
/* PIO15-PIO0 Data Register Bit Definitions */
#define PIO15_DATA 0x8000 /* PIO15 Read Or Change /
#define PIO14_DATA 0x4000 / PIO14 Read Or Change /
#define PIO13_DATA 0x2000 / PIO13 Read Or Changee /
#define PIO12_DATA 0x1000 / PIO12 Read Or Change /
#define PIO11_DATA 0x0800 / PIO11 Read Or Change /
#define PIO10_DATA 0x0400 / PIO10 Read Or Change /
#define PIO9_DATA 0x0200 / PIO9 Read Or Change /
#define PIO8_DATA 0x0100 / PIO8 Read Or Change /
#define PIO7_DATA 0x0080 / PIO7 Read Or Change /
#define PIO6_DATA 0x0040 / PIO6 Read Or Change /
#define PIO5_DATA 0x0020 / PIO5 Read Or Change /
#define PIO4_DATA 0x0010 / PIO4 Read Or Change /
#define PIO3_DATA 0x0008 / PIO3 Read Or Change /
#define PIO2_DATA 0x0004 / PIO2 Read Or Change /
#define PIO1_DATA 0x0002 / PIO1 Read Or Change /
#define PIO0_DATA 0x0001 / PIO0 Read Or Change */
/* PIO31-PIO16 Data Register Bit Definitions */
#define PIO31_DATA 0x8000 /* PIO31 Read Or Change /
#define PIO30_DATA 0x4000 / PIO30 Read Or Change /
#define PIO29_DATA 0x2000 / PIO29 Read Or Change /
#define PIO28_DATA 0x1000 / PIO28 Read Or Change /
#define PIO27_DATA 0x0800 / PIO27 Read Or Change /
#define PIO26_DATA 0x0400 / PIO26 Read Or Change /
#define PIO25_DATA 0x0200 / PIO25 Read Or Change /
#define PIO24_DATA 0x0100 / PIO24 Read Or Change /
#define PIO23_DATA 0x0080 / PIO23 Read Or Change /
#define PIO22_DATA 0x0040 / PIO22 Read Or Change /
#define PIO21_DATA 0x0020 / PIO21 Read Or Change /
#define PIO20_DATA 0x0010 / PIO20 Read Or Change /
#define PIO19_DATA 0x0008 / PIO19 Read Or Change /
#define PIO18_DATA 0x0004 / PIO18 Read Or Change /
#define PIO17_DATA 0x0002 / PIO17 Read Or Change /
#define PIO16_DATA 0x0001 / PIO16 Read Or Change */
/* PIO15-PIO0 Set Register Bit Definitions */
#define PIO15_SET 0x8000 /* PIO15 Set Bit /
#define PIO14_SET 0x4000 / PIO14 Set Bit /
#define PIO13_SET 0x2000 / PIO13 Set Bite /
#define PIO12_SET 0x1000 / PIO12 Set Bit /
#define PIO11_SET 0x0800 / PIO11 Set Bit /
#define PIO10_SET 0x0400 / PIO10 Set Bit /
#define PIO9_SET 0x0200 / PIO9 Set Bit /
#define PIO8_SET 0x0100 / PIO8 Set Bit /
#define PIO7_SET 0x0080 / PIO7 Set Bit /
#define PIO6_SET 0x0040 / PIO6 Set Bit /
#define PIO5_SET 0x0020 / PIO5 Set Bit /
#define PIO4_SET 0x0010 / PIO4 Set Bit /
#define PIO3_SET 0x0008 / PIO3 Set Bit /
#define PIO2_SET 0x0004 / PIO2 Set Bit /
#define PIO1_SET 0x0002 / PIO1 Set Bit /
#define PIO0_SET 0x0001 / PIO0 Set Bit */
/* PIO31-PIO16 Set Register Bit Definitions */
#define PIO31_SET 0x8000 /* PIO31 Set Bit /
#define PIO30_SET 0x4000 / PIO30 Set Bit /
#define PIO29_SET 0x2000 / PIO29 Set Bit /
#define PIO28_SET 0x1000 / PIO28 Set Bit /
#define PIO27_SET 0x0800 / PIO27 Set Bit /
#define PIO26_SET 0x0400 / PIO26 Set Bit /
#define PIO25_SET 0x0200 / PIO25 Set Bit /
#define PIO24_SET 0x0100 / PIO24 Set Bit /
#define PIO23_SET 0x0080 / PIO23 Set Bit /
#define PIO22_SET 0x0040 / PIO22 Set Bit /
#define PIO21_SET 0x0020 / PIO21 Set Bit /
#define PIO20_SET 0x0010 / PIO20 Set Bit /
#define PIO19_SET 0x0008 / PIO19 Set Bit /
#define PIO18_SET 0x0004 / PIO18 Set Bit /
#define PIO17_SET 0x0002 / PIO17 Set Bit /
#define PIO16_SET 0x0001 / PIO16 Set Bit */
/* PIO15-PIO0 Clear Register Bit Definitions */
#define PIO15_CLR 0x8000 /* PIO15 Clear Bit /
#define PIO14_CLR 0x4000 / PIO14 Clear Bit /
#define PIO13_CLR 0x2000 / PIO13 Clear Bite /
#define PIO12_CLR 0x1000 / PIO12 Clear Bit /
#define PIO11_CLR 0x0800 / PIO11 Clear Bit /
#define PIO10_CLR 0x0400 / PIO10 Clear Bit /
#define PIO9_CLR 0x0200 / PIO9 Clear Bit /
#define PIO8_CLR 0x0100 / PIO8 Clear Bit /
#define PIO7_CLR 0x0080 / PIO7 Clear Bit /
#define PIO6_CLR 0x0040 / PIO6 Clear Bit /
#define PIO5_CLR 0x0020 / PIO5 Clear Bit /
#define PIO4_CLR 0x0010 / PIO4 Clear Bit /
#define PIO3_CLR 0x0008 / PIO3 Clear Bit /
#define PIO2_CLR 0x0004 / PIO2 Clear Bit /
#define PIO1_CLR 0x0002 / PIO1 Clear Bit /
#define PIO0_CLR 0x0001 / PIO0 Clear Bit */
/* PIO31-PIO16 Clear Register Bit Definitions */
#define PIO31_CLR 0x8000 /* PIO31 Clear Bit /
#define PIO30_CLR 0x4000 / PIO30 Clear Bit /
#define PIO29_CLR 0x2000 / PIO29 Clear Bit /
#define PIO28_CLR 0x1000 / PIO28 Clear Bit /
#define PIO27_CLR 0x0800 / PIO27 Clear Bit /
#define PIO26_CLR 0x0400 / PIO26 Clear Bit /
#define PIO25_CLR 0x0200 / PIO25 Clear Bit /
#define PIO24_CLR 0x0100 / PIO24 Clear Bit /
#define PIO23_CLR 0x0080 / PIO23 Clear Bit /
#define PIO22_CLR 0x0040 / PIO22 Clear Bit /
#define PIO21_CLR 0x0020 / PIO21 Clear Bit /
#define PIO20_CLR 0x0010 / PIO20 Clear Bit /
#define PIO19_CLR 0x0008 / PIO19 Clear Bit /
#define PIO18_CLR 0x0004 / PIO18 Clear Bit /
#define PIO17_CLR 0x0002 / PIO17 Clear Bit /
#define PIO16_CLR 0x0001 / PIO16 Clear Bit */
/***************************
- Software Timer Registers *
***************************/
#define OFFS_SWTMRMILLI 0x0C60 /* Software Timer Millisecond Count /
#define OFFS_SWTMRMICRO 0x0C62 / Software Timer Microsecond Count /
#define OFFS_SWTMRCFG 0x0C64 / Software Timer Configuration */
#define SWTMRMILLI (MMCR + OFFS_SWTMRMILLI) /* Software Timer
Millisecond Count /
#define SWTMRMICRO (MMCR + OFFS_SWTMRMICRO) / Software Timer
Microsecond Count /
#define SWTMRCFG (MMCR + OFFS_SWTMRCFG) / Software Timer
Configuration */
/*
Software Timer Register Bit Definitions
*/
/* Software Timer Millisecond Count Register Masks */
#define MS_CNT 0xFFFF /* 16-bit Millisecond Count */
/* Software Timer Microsecond Count Register Masks */
#define US_CNT 0xFFFF /* 16-bit Microsecond Count */
/* Software Timer Configuration Register Bit Definitions */
#define SWT_XTAL_FREQ 0x0001 /* Cyrstal Frequency 1 - 33.0Mhz 0 -
33.333Mhz */
/*************************
- General Purpose Timers *
*************************/
#define OFFS_GPTMRSTA 0x0c70 /* GP Timers Status Register /
#define OFFS_GPTMR0CTL 0x0c72 / GP Timer 0 Mode/Control Register /
#define OFFS_GPTMR0CNT 0x0c74 / GP Timer 0 Count Register /
#define OFFS_GPTMR0MAXCMPA 0x0c76 / GP Timer 0 Maxcount Compare A
Register /
#define OFFS_GPTMR0MAXCMPB 0x0c78 / GP Timer 0 Maxcount Compare B
Register /
#define OFFS_GPTMR1CTL 0x0c7A / GP Timer 1 Mode/Control Register /
#define OFFS_GPTMR1CNT 0x0c7C / GP Timer 1 Count Register /
#define OFFS_GPTMR1MAXCMPA 0x0c7E / GP Timer 1 Maxcount Compare
Register A /
#define OFFS_GPTMR1MAXCMPB 0x0c80 / GP Timer 1 Maxcount Compare B
Register /
#define OFFS_GPTMR2CTL 0x0c82 / GP Timer 2 Mode/Control Register /
#define OFFS_GPTMR2CNT 0x0c84 / GP Timer 2 Count Register /
#define OFFS_GPTMR2MAXCMPA 0x0c8E / GP Timer 2 Maxcount Compare A
Register */
#define GPTMRSTA (MMCR + OFFS_GPTMRSTA) /* GP Timers Status Register /
#define GPTMR0CTL (MMCR + OFFS_GPTMR0CTL) / GP Timer 0 Mode/Control
Register /
#define GPTMR0CNT (MMCR + OFFS_GPTMR0CNT) / GP Timer 0 Count Register /
#define GPTMR0MAXCMPA (MMCR + OFFS_GPTMR0MAXCMPA) / GP Timer 0 Maxcount
Compare A Register /
#define GPTMR0MAXCMPB (MMCR + OFFS_GPTMR0MAXCMPB) / GP Timer 0 Maxcount
Compare B Register /
#define GPTMR1CTL (MMCR + OFFS_GPTMR1CTL) / GP Timer 1 Mode/Control
Register /
#define GPTMR1CNT (MMCR + OFFS_GPTMR1CNT) / GP Timer 1 Count Register /
#define GPTMR1MAXCMPA (MMCR + OFFS_GPTMR1MAXCMPA) / GP Timer 1 Maxcount
Compare Register A /
#define GPTMR1MAXCMPB (MMCR + OFFS_GPTMR1MAXCMPB) / GP Timer 1 Maxcount
Compare B Register /
#define GPTMR2CTL (MMCR + OFFS_GPTMR2CTL) / GP Timer 2 Mode/Control
Register /
#define GPTMR2CNT (MMCR + OFFS_GPTMR2CNT) / GP Timer 2 Count Register /
#define GPTMR2MAXCMPA (MMCR + OFFS_GPTMR2MAXCMPA) / GP Timer 2 Maxcount
Compare A Register */
/*
General Purpose Register Bit Definitions
*/
/* Timer Status Register bit definitions */
#define GPTSTA_T2_INT_STA 0x04 /* [2] s/w writes a ‘1’ to clear the
bit Timer 2 Interrupt Status bit*/
#define GPTSTA_T1_INT_STA 0x02 /* [1] * " * Timer 1 Interrupt Status
bit /
#define GPTSTA_T0_INT_STA 0x01 / [0] * " * Timer 0 Interrupt Status
bit /
/ Timer 0 & 1 & 2 Mode/Control Register bit definitions */
#define GPTCON_ENB 0x8000 /* [15] timer enable bit /
#define GPTCON_P_ENB_WR 0x4000 / [14] Timer Permit Enable Bit Wri