hi
I am trying to use pci_write_config32() write to registers on my
device to set Interrupts on it. I have with me the offsets for the
required registers.
The question I have is:
pci_write_config32 lets me specify an offset into the PCI
configuration space for the device; whereas register offsets are
relative to the base address assigned to the card by, if I understand
it correctly, the system BIOS.
Is there a way for me to know the offset of my card registers relative
to the PCI configuration space? Is there a PCI configuration space
standard which is followed, and can be used to determine the register
offsets?
Knowing this will be of help to me in my routine.
Thanks
Ninad
Take a look at the pci.h header file. This will give you all the offsets
into the PCI configuration space. The BaseAddressRegisters will hold the
memory and/or I/O addresses of your device.
“ninadpradhan” <ninad.pradhan@gmail-dot-com.no-spam.invalid> wrote in
message news:e8kt6p$73r$1@inn.qnx.com…
hi
I am trying to use pci_write_config32() write to registers on my
device to set Interrupts on it. I have with me the offsets for the
required registers.
The question I have is:
pci_write_config32 lets me specify an offset into the PCI
configuration space for the device; whereas register offsets are
relative to the base address assigned to the card by, if I understand
it correctly, the system BIOS.
Is there a way for me to know the offset of my card registers relative
to the PCI configuration space? Is there a PCI configuration space
standard which is followed, and can be used to determine the register
offsets?
Knowing this will be of help to me in my routine.
Thanks
Ninad
Hugh
Thanks for the tip. I took a look at the header file, and it helped me
get a better idea of the PCI interface used by QNX. However, my
question was not quite answered, and it is possible that this is
because i didn’t understand the header file in the way I should have.
Forgive my ignorance…
What I wanted to know was: there is this device register I need to
access, which is at an offset of 0 bytes from the Base Address. To
use pci_read/write_config32, I need to specify the offset into the
configuration space for this register.
What the pci_dev_info struct defined by hw/pci.h seems to contain is a
method of getting the Base Address. How do I get the register offset
into the configuration space? Does PCI use a standard by which, for
example, the first 20 bytes contain PCI card related information,
after which the PCI Card registers (those which users can read
from/write to) are located?By that logic, byte 21 would be the first
byte for my device register, and hence the offset parameter in the
pci_read_config32() command would be 21?
Regards
Ninad
The Base Address register contains the address of your device register. If
it is an I/O address (which you can find out about by using the PCI_IS_IO()
macro) you then use the mmap_device_io() function to map this address. Once
you have done this, you can use the in* and out* instructions to read/write
different offsets within your device’s I/O space using the mapped address
plus an offset.
If the Base Address is a memory address, then you use the
mmap_device_memory() function to map the address, then use this mapped
address as a memory pointer into you device’s register space.
“ninadpradhan” <ninad.pradhan@gmail-dot-com.no-spam.invalid> wrote in
message news:e8nhij$2hb$1@inn.qnx.com…
Hugh
Thanks for the tip. I took a look at the header file, and it helped me
get a better idea of the PCI interface used by QNX. However, my
question was not quite answered, and it is possible that this is
because i didn’t understand the header file in the way I should have.
Forgive my ignorance…
What I wanted to know was: there is this device register I need to
access, which is at an offset of 0 bytes from the Base Address. To
use pci_read/write_config32, I need to specify the offset into the
configuration space for this register.
What the pci_dev_info struct defined by hw/pci.h seems to contain is a
method of getting the Base Address. How do I get the register offset
into the configuration space? Does PCI use a standard by which, for
example, the first 20 bytes contain PCI card related information,
after which the PCI Card registers (those which users can read
from/write to) are located?By that logic, byte 21 would be the first
byte for my device register, and hence the offset parameter in the
pci_read_config32() command would be 21?
Regards
Ninad
Hugh,
Thanks. I am at a point where I can try the in/out commands and memory
mapping.
Out of curiosity, why do we have six BaseAddress registers? For my
device, the first register stores an address, but the rest are all
zero. In what kind of devices may we see more than one being used?
There are six base address registers because that is what the PCI spec calls
for! Whether designers use one or all of them is up to the hardware
manufacturer.
“ninadpradhan” <ninad.pradhan@gmail-dot-com.no-spam.invalid> wrote in
message news:e90hrt$74j$1@inn.qnx.com…
Hugh,
Thanks. I am at a point where I can try the in/out commands and memory
mapping.
Out of curiosity, why do we have six BaseAddress registers? For my
device, the first register stores an address, but the rest are all
zero. In what kind of devices may we see more than one being used?
ninadpradhan <ninad.pradhan@gmail-dot-com.no-spam.invalid> wrote:
Hugh,
Thanks. I am at a point where I can try the in/out commands and memory
mapping.
Out of curiosity, why do we have six BaseAddress registers? For my
device, the first register stores an address, but the rest are all
zero. In what kind of devices may we see more than one being used?
I known I’ve seen devices with 3 – a graphics card with a set of
control registers as an IO range, and two different (both largish)
memory ranges.
Hm… a multi-head ethernet card, could have several, IO and Memory
for 2 or 3 channels, each in a different range, for instance.
-David
David Gibbs
QNX Training Services
dagibbs@qnx.com