Hello.
My 32-bit ARM9 RISC SoC has just 1 interrupt controller with 29 interrupt
sources.
If I understood the cascaded vector’s meaning well, I doesn’t need cascaded
vectors.
Is it right ?
const static struct startup_intrinfo intrs[] = {
{ _NTO_INTR_CLASS_EXTERNAL, // vector
base
32, //
number of vectors
_NTO_INTR_SPARE, //
cascade vector
0, //
CPU vector base
0, //
CPU vector stride
0, //
flags
{ INTR_GENFLAG_LOAD_SYSPAGE, 0, &interrupt_id_jaguar2
},
{ INTR_GENFLAG_LOAD_SYSPAGE |
INTR_GENFLAG_LOAD_INTRMASK, 0, &interrupt_eoi_jaguar2 },
&interrupt_mask_jaguar2, // mask callout
&interrupt_unmask_jaguar2, // unmask callout
0, // config
callout
}
The upper source code is my startup_intrinfo but I think its source code has
the problem.
I think that there is some proper value for a cascade vector instead of
_NTO_INTR_SPACE.
Actually, I didn’t understand the meaning of the cascade vector.
Please help me.
Best regards.
Pusik.