I am not able to understand how does my source code or makefile identifies the target I am trying to compile the code for. Neither there is any command for this in makefile and nor it is specified anywhere in my source code. I havent found any such environment variable also regarding the same.
When I run make for the attached Makefile following error comes:
cc: /usr/lib/gcc-lib/ntox86/2.95.3/cc1 error 33
Pls suggest me the solution.
could you post your makefile. Makefiles have build in rules and it’s probably what you are seeing.
the contents of makefile are:
LIB_DIR = …/lib
CFLAGS += -w5 -I…/inc -I…/include
LDFLAGS+= -lc -lmath -lwat
all: audio
install: all
cp audio …/bin
audio: audio.o audiohw.o …/lib/libwat.a
audio.o: audio.h audiohw.h …/disk/disk.h audio.c audiohw.c
clean:
rm -f *.o audio
clobber:
rm -f *.o audio
The couple lines proceeding this:
When I run make for the attached Makefile following error comes:
cc: /usr/lib/gcc-lib/ntox86/2.95.3/cc1 error 33
would be helpful - to see what actually fails. You may need a line like this as well:
audiohw.o: audiohw.c
I think the error you are seeing are “normal” compiler error, check your source code Reading your original question, as I said the reason why make calls cc event though you didn’t specify it is because you have implicitly used the default rules. When you specify audio.o: … Make knows by default .o are build from c file thus required cc. If you were to specify a command such as
audio.o: audio.c
echo foo
Then audio.o would NOT be build because make would invoke the echo command instead of the buildin definition.
Does that answer your question?