Automation for compilation of QNX projects

HI All,
I need to manage so many QNX projects for entire build cycle. Is there any command line options to compile the QNX Project. Basically i need to create a batch file for compilation of multiple projects in sequence. Please suggest some way to resolve my problem.

Is there anything that the shell and make can’t handle?

make file would be fine. If i would be able to compile 3 different QNX projects using a single make file. Can you please elaborate how to create make file for multiple project compilation
For example, First, second and third are the name of QNX projects.

Garyritu,

This is really a make question not a QNX question.

Here is a cut down example of a Makefile we use

# Set up an export variable for handling release vs debug compilation.
# A basic 'make' call builds debug code while a 'make release' builds
# optimized code.
#
ifeq ($(MAKECMDGOALS), release)
  export WITHOUT_DEBUG_SYMBOLS=1
else
  export WITHOUT_DEBUG_SYMBOLS=0
endif

# Get the list of options for compilation and linking
#
include Makefile.Flags

# All is set up to build all Projects. Release is just a call to all with an
# export flag set to build optimized code
#
all: Projects

release: all

# The list of target project directories containing code for clean and build
# commands.
#
ProjectList = $(HOME)/First \
	   	    $(HOME)/Second \
			$(HOME/Third \


# Make 'targets' follow:
#
# Projects builds all the various projects
#
Projects:
	@ for dir in $(ProjectList) \
	 ; do \
		echo Building $$dir ; \
		make -C $$dir \
	; done

# clean removes all executables, libraries and object files
#
clean:
	@ for dir in $(ProjectList) \
	 ; do \
		echo Cleaning $$dir ; \
		make -C $$dir clean \
	; done
	
	- rm libs/debug/*.a libs/release/*.a

# Depend logic here
#
depend:
	@echo "Put your depend logic here"
    

The part of Makefile.flags that would be of interest to you is:

# Set compiler to gcc compiler version 3.3.5
#
CC = qcc -V3.3.5,gcc_ntox86_cpp
CXX = qcc -V3.3.5,gcc_ntox86_cpp
LD = qcc -V3.3.5,gcc_ntox86_cpp

# Defines some paths where source, include and library files are
# located under each project
#
OBJDEBUGDIR = ../obj/debug
OBJRELEASEDIR = ../obj/release
EXEDEBUGDIR = ../bin/debug
EXERELEASEDIR = ../bin/release
LIBCOMMONDEBUGDIR = ../../../libs/debug
LIBDEBUGDIR = ../../libs/debug
LIBCOMMONRELEASEDIR = ../../../libs/release
LIBRELEASEDIR = ../../libs/release

ifeq ($(WITHOUT_DEBUG_SYMBOLS), 1)
OBJDIR = $(OBJRELEASEDIR)
LIBCOMMONDIR = $(LIBCOMMONRELEASEDIR)
LIBDIR = $(LIBRELEASEDIR)
EXEDIR = $(EXERELEASEDIR)
else
OBJDIR = $(OBJDEBUGDIR)
LIBCOMMONDIR = $(LIBCOMMONDEBUGDIR)
LIBDIR = $(LIBDEBUGDIR)
EXEDIR = $(EXEDEBUGDIR)
endif

# Defines a list of filenames which correspond to the C (C_SRC) and
# C++ (CXX_SRC) source files in the current directory, and from this
# constructs a list of the corresponding object files (C_OBJ & CXX_OBJ)
#
C_SRC = $(wildcard *.c)
C_DEP = $(C_SRC:.c=.d)
C_OBJ = $(patsubst %.c, $(OBJDIR)/%.o, $(filter %.c, $(C_SRC)))
CXX_SRC = $(wildcard *.cpp)
CXX_DEP = $(CXX_SRC:.cpp=.d)
CXX_OBJ = $(patsubst %.cpp, $(OBJDIR)/%.o, $(filter %.cpp, $(CXX_SRC)))

# Combined lists of C and C++ source and object files
#
SRC = $(C_SRC) $(CXX_SRC)
OBJ = $(C_OBJ) $(CXX_OBJ)
DEP = $(C_DEP) $(CXX_DEP)

# Standard flag setting for usage when the C & C++ compiler is invoked
# as well as the archive compiler (AR) and the linker (LD)
# LDFLAGS should be used for linker flags, while LDLIBS should be used
# to declared additional libraries to link against (via the -l flag).
#
ifeq ($(WITHOUT_DEBUG_SYMBOLS), 1)
CFLAGS = -lang-c++ -O -D_PTHREADS=1 -w9 -Wall -Werror -Wno-deprecated
else
CFLAGS = -lang-c++ -D_PTHREADS=1 -g -w9 -Wall -Werror -Wno-deprecated
endif
CXXFLAGS = $(CFLAGS)

LIBFLAGS = -Vgcc_ntox86 -A

ifeq ($(WITHOUT_DEBUG_SYMBOLS), 1)
LDFLAGS = -lang-c++ -O -M -D_PTHREADS=1 -l m
else
LDFLAGS = -lang-c++ -g -M -D_PTHREADS=1 -l m
endif
LDLIBS = 

endif

Inside each of your projects (First, Second, Third) you’ll need another Makefile that does the work in those projects (I assume you already have those Makefiles created and working. Our projects themselves contain multiple directories. So the top level Make in each project looks like the Makefile I showed above only it lists the directories of that particular project). Essentially what you are doing is recursively calling Make in a sub directory which itself can call more Make’s in yet more sub directories.

If you have specific needs for a project then you may not want a Makefile.Flags at the top level but rather have one in each project and include it in the Makefile in that project directory.

Tim

Thanks for detailed explaination about the make file.

Hi All,
I am getting errors in automatic compilation of multiple projects.
Error **** missing Serparator. Stop. Please have a look what i did …

# Set up an export variable for handling release vs debug compilation. 

A basic ‘make’ call builds debug code while a ‘make release’ builds

optimized code.

ifeq ($(MAKECMDGOALS), release)
export WITHOUT_DEBUG_SYMBOLS=1
else
export WITHOUT_DEBUG_SYMBOLS=0
endif

Get the list of options for compilation and linking

#include Makefile.Flags

All is set up to build all Projects. Release is just a call to all with an

export flag set to build optimized code

all: Projects

release: all

The list of target project directories containing code for clean and build

commands.

ProjectList = C:/QNXProjects/Hello1
C:/QNXProjects/Hello2 \

Make ‘targets’ follow:

Projects builds all the various projects

Projects:
echo u r in projects
$(ProjectList) \
; do \
echo Building $$dir ; \
make -C $$dir \
; done

clean removes all executables, libraries and object files

clean:
@ for dir in $(ProjectList) \
; do \
echo Cleaning $$dir ; \
make -C $$dir clean \
; done

  • rm libs/debug/.a libs/release/.a

Gary,

It’s hard to see where things are wrong because it’s not easy to see spaces vs tabs in this kind of format.

Can you do a ‘make -d’ and see where it stops. That should show the line that has the problem.

Otherwise the 2 lines that look suspicious (can’t tell due to space/tab or if you have 1 line broken into 2) are:

  1. C:/QNXProjects/Hello2 \ // Should be tabbed over
  2. echo u r in projects
    $(ProjectList) \ // Should be 1 line, not 2

Tim

The list of target project directories containing code for clean and build

commands.

ProjectList = C:/QNXProjects/Hello1 / C:/QNXProjects/Hello2 /

Make ‘targets’ follow:

Projects builds all the various projects

Projects: $(ProjectList) \ this line is giving error **** missing rule before commands. Stop
; do \
echo Building $$dir ; \
make -C $$dir \
; done

Gary,

You appear to be missing this line:

@ for dir in $(ProjectList) \

Tim

I have added above mentioned line but now i am getting following error

make: **** No Rule to make target ‘C:/QNXProjects/Hello1’, needed by ‘Projects’. Stop

I have given possible commands to compile code using cmd line. like
cmd > make
cmd > make all
cmd > make release
cmd > Projects

Gary,

Make sure your ‘Projects:’ line is identical to what I had

# Make 'targets' follow:
#
# Projects builds all the various projects
#
Projects:
   @ for dir in $(ProjectList) \
    ; do \
      echo Building $$dir ; \
      make -C $$dir \
   ; done 

If it is then in C:/QNXProjects/Hello1 you need a Makefile for the Hello1 project. Otherwise there is nothing to make. So is there a Makefile in C:/QNXProjects/Hello1

Some place in your Makefile you have mis-copied something I did in my original post.

Tim