PCI I/O space Acess enable

QNX DEVELOPERS Realtime and Embedded
1

Hi all,

How to enable PCI I/O space access & memory space access enable using pci_write_config32()?

i am using qnx 6.5.0.
following this is the result of pci -vvv

Class = Bridge (Other)
Vendor ID = 10b5h, PLX Technology, Inc.
Device ID = 1024h, Acromag, Inc. IndustryPack Carrier Card
PCI index = 0h
Class Codes = 068000h
Revision ID = 1h
Bus number = 4
Device number = 15
Function num = 0
Status Reg = 280h
Command Reg = 0h
I/O space access disabled
Memory space access disabled
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled
Palette Snooping disabled
Parity Error Response disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
PCI INTx enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 10h un-cacheable
Subsystem Vendor ID = 10b5h
Subsystem ID = 1024h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 11
CPU Interrupt = bh
Device Dependent Registers:
0x040: 0000 0000 0000 0000 0000 0000 0000 0000
…
0x0f0: 0000 0000 0000 0000 0000 0000 0000 0000

PCI server & read config info are OK.i am using mmap_device_memory() for mapping address.
how to enable IO’s ?
please help me to sort out this problem …

Thanks,
Raj.

2

mmap_device_io()

3

I have tried using mmap_device_io() , but still problem not solved. PCI I/O access not enabled .

Thanks,
Raj.

4

Can you post your code.

Are you for example checking all the return codes for errors?

Tim

5

Hi …
I am using this program …
/* Connect to the PCI server */
phdl = pci_attach( 0 );
if( phdl == -1 ) {
fprintf( stderr, “Unable to initialize PCI\n” );

    return EXIT_FAILURE;
}

/* Initialize the pci_dev_info structure */
memset( &inf, 0, sizeof( inf ) );
pidx = 0;
inf.VendorId = PCI_VENDOR_ID_ADAPTEC;
inf.DeviceId = PCI_DEVICE_ID_ADAPTEC_2940F;

hdl = pci_attach_device( NULL, PCI_INIT_ALL, pidx, &inf );
if( hdl == NULL ) {
    fprintf( stderr, "Unable to locate adapter\n" );
} else {
    /* Do something to the adapter */
    pci_detach_device( hdl );
}

/* Disconnect from the PCI server */
pci_detach( phdl );

still PCI IO’s are not enabled IN QNX 6.5.0 …

6

Where is the mmap_device_io code?

And what are you trying to do with this device that you are sure isn’t working?

Tim

7

Dear Tim,

The actual problem is this in QNX 6.5.0
I connected a pci based I/O device to my PC, it is showing


I/O space access disabled
Memory space access disabled

I want this I/O space access & memory space access enabled . How to enable this ?

Thanks…
Raj.

8

I believe enabling is a function of the BIOS not of QNX. QNX doesn’t allocated resource or ena ble the hardware. Or it may be the way the card is setup it informs the BIOS not to enable it or the BIOS couldn’t enable it for somereason.

I once had a card like this when put in a model of IBM computer it wouldn’t get enabled, while it some other model it was working fine. The work around was to enable it manually by flipping a bits in the PCI register command set

// those lovely IBM required a patch because for some reason they will disable the card.
	
if ( Model == 'd' || Model == 'c' ) 
{
	const unsigned short  CommandId = 0x116;
		
	if ( pci_write_config16( PciDev.busNum, PciDev.devFuncNum, offsetof( struct _pci_config_regs, Command ),	1, (char *)&CommandId) != PCI_SUCCESS )
	{
		perror("Can't write config");
	}
}
9

Tnx for your reply… this works for me .But still PCI I/O space in disabled mode only…
But Read/Write options are working fine…

One more thing is I had 3 same I/O cards on PCI bus. But when i see in “PCI -vvv” device list its only showing 1 card. Its not showing rest of cards…

Any solutions please…

10

Yes, I saw this same issue with the Acromag APC8620 Carrier board. I am using a PIC-H61 PICMG1.3 CPU card.
Getting Command code of 0 back, indicating IO access disabled and memory access disabled. Here is the fix that worked
for me:

pci_read_config32( brd->bus, brd->dev_func, 0, 16, (void *)&pci_regs );   // brd is carrier board structure after pci_attach

if (pci_regs.Command != 3)
{
	pci_regs.Command = 3;		// enable IO and MMAP writes. bit 0 is IO; bit 1 is memory
	fprintf( stderr, "config Command fix-up write try \n");	// command isn't correct; need to write correct value to it 

	status = pci_write_config32( brd->bus, brd->dev_func, 0, 2, (void *)&pci_regs );  // two reg's covers Command
	fprintf( stderr, "pci_write_config32 status %x \n", status );					// check status of write

	pci_read_config32( brd->bus, brd->dev_func, 0, 16, (void *)&pci_regs );		// read again and see if fix worked !

	fprintf( stderr, "config vendorID %x \n", pci_regs.Vendor_ID);
	fprintf( stderr, "config deviceID %x \n", pci_regs.Device_ID);
	fprintf( stderr, "config Status %x \n", pci_regs.Status);
	fprintf( stderr, "config Command %x \n", pci_regs.Command);                            // want to see value of 3 now
	fprintf( stderr, "config subVend ID %x \n", pci_regs.Sub_Vendor_ID);
	fprintf( stderr, "config subSys ID %x \n", pci_regs.Sub_System_ID);
}