I added the following code at the end of cstart.S
/*
* Set the translation table base
*/
ldr r0, =_arm_board_ttb // set start of Translation Table base
orr r0, r0, #((3 << 3) | 3)
mcr p15, 0, r0, c2, c0, 0
/* Enable the MMU, I-Cache and D-Cache */
mrc p15, 0, r0, c1, c0, 0
BIC r0, r0, #(1 << 12) // enable I Cache
BIC r0, r0, #(1 << 2) // enable D Cache
BIC r0, r0, #(1 << 0) // enable MMU
mcr p15, 0, r0, c1, c0, 0
A code example of TI JACINTO with Cortex-A8 to use the info Caches.
AFTER:
D cache is disabled
I cache is enabled
MMU is disabled
CP15 control register = 0x00c5187c
CP15 control register C bit is enabled
CP15 aux control register = 0x00000042
CP15 aux control register L2EN bit is enabled
L2 is enabled
BEFORE:
D cache is enabled
I cache is enabled
MMU is enabled
CP15 control register = 0x00c5187c
CP15 control register C bit is enabled
CP15 aux control register = 0x00000042
CP15 aux control register L2EN bit is enabled
L2 is enabled
But Decompressing still is slower. I forgot to add some routine?
Link to my cstart.S → pastebin.com/gipwTiQn